Nuno Cavaco Gomes Horta

Nuno Horta

Academic position:	Associate Professor
Joining date:	01-01-1999
Roles in IT:	Senior Researcher
Thematic Line:	Basic Sciences and Enabling Technologies
Group:	Integrated Circuits - Lx

Email: Send Email
Address: IT – Lisboa
Instituto Superior Técnico - Torre Norte - Piso 10
Av. Rovisco Pais, 1
1049 - 001 Lisboa
Tel: +351 21 841 84 54
Fax: +351 21 841 84 72

https://www.orcid.org/0000-0002-1687-1447

RESEARCHER ID SCOPUS SCHOLAR

Bio

Nuno Horta (S’89–M’97–SM’11) received the Licenciado, MSc, PhD and Habilitation degrees in electrical engineering from Instituto Superior Técnico (IST), University of Lisbon, Portugal, in 1989, 1992, 1997 and 2014, respectively. He is an Associate Professor at IST Electrical and Computer Engineering Department. He is a Senior Researcher at Instituto de Telecomunicações, where he is the head of the Integrated Circuits Group. He has supervised more than 90 post graduation works between MSc and PhD theses. He has authored or co-authored more than 150 publications as books, book chapters, international journals papers and conferences papers. He has also participated as researcher or coordinator in several National and European R&D projects. He was General Chair of AACD 2014, PRIME 2016 and SMACD 2016 and was member of the organizing and technical program committees of several other conferences, e.g., IEEE ISCAS, IEEE LASCAS, DATE, NGCAS, etc. He is Associated Editor of Integration, The VLSI Journal, from Elsevier, and usually acts as reviewer of several prestigious publications, e.g., IEEE TCAD, IEEE TEC, IEEE TCAS, ESWA, ASC, etc. His research interests are mainly in analog and mixed-signal IC design, analog IC design automation, soft computing and data science.

Scientific Achievements

Degrees

Agregação, Instituto Superior Técnico, 09-09-2014
PhD, Instituto Superior Técnico, 24-07-1997
MSc, Instituto Superior Técnico, 30-11-1992
Licenciatura, Instituto Superior Técnico, 31-07-1989

Affiliations

ACM - Association for Computing Machinery, 01-11-2004, Senior Member
Instituto Superior Técnico, 01-03-1998, Associate Professor with Habilitation
Instituto de Telecomunicações, 01-09-1997, Senior Researcher
IEEE - Institute of Electrical and Electronics Engineers, 01-01-1991, Senior Member

Expertise Topics

Electronic Design Automation
Computer Architectures
Computational Intelligence
Computational Finance

Academic Activities

10Lecture courses

Arquitectura de Computadores, , Mestrado em Engenharia Electrotécnica e de Computadores
Sistemas Digitais, , Mestrado em Engenharia Electrotécnica e de Computadores
ANALOG AND MIXED-SIGNAL IC DESIGN AUTOMATION , , PhD Elect e Computadores
Arquitecuras Avançadas de Computadores, , Mestrado em Engenharia Electrotécnica e de Computadores
Multi-Objective Optimization Using Evolutionary, Instituto Superior Técnico, PhD Program in Electrical and Computer Engineering
Analog IC Design Automation, Instituto Superior Técnico, PhD Program in Electrical and Computer Engineering
Computer Architecture, , Integrated Master Degree (MSc) in Electrical and Computer Engineering
Computer Architecture, Instituto Superior Técnico, Integrated Master Degree (MSc) in Electrical and Computer Engineering
Digital Systems, Instituto Superior Técnico, Integrated Master Degree (MSc) in Electrical and Computer Engineering
Advanced Computer Architectures, Instituto Superior Técnico, Integrated Master Degree (MSc) in Electrical and Computer Engineering

9Supervision of PhD theses

As Co-supervisor

Organic Integrated Circuits, Research Grant, Samuel Pinto, Concluded 07-2006
Organic Integrated Circuits-II, Research Grant, Vitor Pelado, Concluded 07-2006

Publications

18Books

R. Vieira, R. P. Póvoa, N. Lourenço, N. Horta, Tunable Low-Power Low-Noise Amplifier For Healthcare Applications, Springer International Publishing, Lisboa, 2021,
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A. Canelas, J.G. Guilherme, N. Horta, Yield-Aware Analog IC Design and Optimization in Nanometer-scale Technologies, Springer International Publishing, Switzerland AG, 2020,
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A. Gusmão, N. Horta, N. Lourenço, R. M. Martins, Analog IC Placement Generation via Neural Networks from Unlabeled Data, Springer International Publishing, Lisbon, 2020,
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S. Sarmento, N. Horta, A Machine Learning Based Pairs Trading Investment Strategy, Springer, Gewerbestrasse 11, 6330 Cham, Switzerland, 2020,
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J. Rosa, D. Guerra, N. Horta, R. M. Martins, N. Lourenço, Using Artificial Neural Networks for Analog Integrated Circuit Design Automation, Springer, Gewerbestrasse 11, 6330 Cham, Switzerland, 2020,
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R. P. Póvoa, JG Goes, N. Horta, A New Family of Cascode-Free Amplifiers with High Energy-Efficiency and Improved Gain, Springer, Cham, Switzerland, 2019,
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M. Mauro, J.G. Guilherme, N. Horta, Logarithmic Voltage-to-Time Converter for Analog-to-Digital Signal Conversion, Springer International Publishing AG Springer Nature, Cham Switzerland, 2019,
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J. Baúto, R. Neves, N. Horta, Parallel Genetic Algorithms for Financial Pattern Discovery Using GPUs, Springer, lisboa, 2018,
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J. Leitao, R. Neves, N. Horta, Identifying Patterns in Financial Markets: New Approach Combining Rules Between PIPs and SAX, Springer, Lisboa, 2018,
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N. Lourenço, R. M. Martins, N. Horta, Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects, Springer International Publishing, Switzerland, 2017,
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R. M. Martins, N. Lourenço, N. Horta, Analog Integrated Circuit Design Automation – Placement, Routing and Parasitic Extraction Techniques, Springer International Publishing, Switzerland, 2017,
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A. Silva Silva, R. Neves, N. Horta, Portfolio Optimization Using Fundamental Indicators Based on Multi-Objective EA, Springer, Heidelberg, 2016,
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R. Lourenço Lourenço, N. Lourenço, N. Horta, AIDA-CMK: Multi-Algorithm Optimization Kernel applied to Analog IC Sizing, Springer, Heidelberg, New York, London, 2015,
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F. Rocha, R. M. Martins, N. Lourenço, N. Horta, Electronic Design Automation of Analog ICs combining Gradient Models with Multi-Objective Evolutionary Algorithms, Springer, Heidelberg, 2014,
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A. Gorgulho Gorgulho, R. Neves, N. Horta, Intelligent Financial Portfolio Composition based on Evolutionary Computation Strategies, Springer, Heidelberg, 2013,
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A. Canelas, R. Neves, N. Horta, Investment Strategies Optimization based on a SAX-GA Methodology, Springer, Heidelberg, 2013,
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R. M. Martins, N. Lourenço, N. Horta, Generating Analog IC Layouts with LAYGEN II, Springer, n/a, 2013,
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M.B. Barros, J.G. Guilherme, N. Horta, Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques, Springer, Berlin, 2010,
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10Books Chapters

J. Pinto, R. Neves, N. Horta, MULTI-OBJECTIVE OPTIMIZATION OF TRADING STRATEGIES USING GENETIC ALGORITHMS IN UNSTABLE ENVIRONMENTS, Chapter in, New Developments in Evolutionary Computation Research, Nova Publisher, Hauppauge, New York., 2015
J.G. Guilherme, N. Horta, Automatic Layout Optimizations for Integrated MOSFET Power Stages, Chapter in, Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, Springer, Switzerland, 2015
C. Silva, J.G. Guilherme, N. Horta, Nonlinearities Behavioral Modeling and Analysis of Pipelined ADC Building Blocks, Chapter in, Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, Springer, Switzerland, 2015
N. Leite Leite, R. Neves, N. Horta, F. Melício Melício, A.C.R. Rosa, Solving a Capacitated Exam Timetabling Problem Instance using a Bi-objective NSGA-II, Chapter in, Studies in Computational Intelligence, Kurosh Madani, António Dourado, Agostinho Rosa, Joaquim Filipe, Springer, Heidelberg, 2014
A. Canelas, R. M. Martins, R. P. Póvoa, N. Lourenço, J.G. Guilherme, N. Horta, Enhancing an Automatic Analog IC Design Flow by using a Technology-Independent Module Generator, Chapter in, Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Maria Helena Fino, IGI global, Medical Information Science Reference, 2014
R. P. Póvoa, N. Lourenço, A. Canelas, R. M. Martins, N. Horta, Synthesis of LC-Oscillators using Rival Multi-Objective/Multi-Constraint Optimization Kernels, Chapter in, Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Maria Helena Fino, IGI global, Medical Information Science Reference, 2014
N. Lourenço, R. M. Martins, M.B. Barros, N. Horta, Analog Circuit Design based on Robust POFs using an Enhanced MOEA with SVM Models, Chapter in, Analog/RF and Mixed-Signal Circuit Systematic Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Rafael Castro-Lopez, Springer, Heidelberg, 2013
P. Parracho Parracho, A. Canelas, R. Neves, N. Horta, Optimized Uptrend and Downtrend Pattern Templates for Financial Markets Trading Based on a GA Kernel, Chapter in, Financial Markets: Recent Developments, Emerging Practices and Future Prospects, Mohsen Bahmani-Oskooee and Sahar Bahmani, Nova Publisher, 2013
M. Mauro, N. Horta, AMS Synthesis Using Symbolic Methods, Chapter in, Design of Analog Circuits through Symbolic Analysis, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Francisco V. Fernández, Bentham Science Publishers, 2012
N. Horta, C.A. Leme, J.E. Franca, Automated High Level Synthesis of Data Conversion Systems, Chapter in, ANALOGUE-DIGITAL ASICs circuit techniques, design tools and applications, IEE - Peter Peregrinus, IEE Press, 1991

51Papers in Journals

A. Gusmão, R. P. Póvoa, N. Horta, N. Lourenço, R. M. Martins, DeepPlacer: A custom integrated OpAmp placement tool using deep models, Applied Soft Computing Journal, Vol. 115, No. n/a, pp. 108188 - 108188, January, 2022,
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A. Canelas, F. Passos, N. Lourenço, R. M. Martins, E. Roca, R. Castro-López, N. Horta, F. V. Fernandez Fernandez, Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs, IEEE Access, Vol. 9, No. 1, pp. 124152 - 124164, September, 2021,
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R. M. Martins, N. Lourenço, R. P. Póvoa, N. Horta, Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing, Engineering Applications of Artificial Intelligence, Vol. 98, No. n/a, pp. 104102 - 104102, February, 2021,
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S. Sarmento, N. Horta, Enhancing a Pairs Trading strategy with the application of Machine Learning, Expert Systems with Applications, Vol. 158, No., pp. 113490 - 113490, November, 2020 | Full text (PDF 2 MBs) | BibTex
R. M. Martins, N. Lourenço, N. Horta, J. Y. Yin, P. M. Mak, R. P. M. Martins, Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 67, No. 11, pp. 3965 - 3977, November, 2020,
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R. P. Póvoa, A. Canelas, R. M. Martins, N. Lourenço, N. Horta, JG Goes, A new family of CMOS inverter-based OTAs for biomedical and healthcare applications, Integration, the VLSI Journal, Vol. 71, No. 0, pp. 38 - 48, March, 2020 | BibTex
F. Passos, E. Roca, R. M. Martins, N. Lourenço, S. Ahyoune Ahyoune, J. S. Sieiro, R. Castro-López, N. Horta, F. V. Fernandez Fernandez, Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology, IEEE Access, Vol. 8, No. -, pp. 51601 - 51609, March, 2020 | BibTex
R. P. Póvoa, R. Arya, A. Canelas, F. Passos, R. M. Martins, N. Lourenço, N. Horta, Sub-μW Tow-Thomas based biquad filter with improved gain for biomedical applications, Microelectronics Journal, Vol. 95, No. 0, pp. 104675 - 104675, January, 2020 | BibTex
V. Camacho, N. Horta, M. L. Lopes, C. Oliveira, Optimizing earthquake design of reinforced concrete bridge infrastructures based on evolutionary computation techniques, Structural and Multidisciplinary Optimization, Vol. 61, No. 3, pp. 1087 - 1105, November, 2019 | BibTex
D. Moniz, J. M. Pedro, N. Horta, J. J. O. Pires, Multi-objective framework for cost-effective OTN switch placement using NSGA-II with embedded domain knowledge, Applied Soft Computing Journal, Vol. 83, No. 105608, pp. - - -, October, 2019 | BibTex
R. P. Póvoa, N. Lourenço, R. M. Martins, A. Canelas, N. Horta, JG Goes, A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 1, No. 1, pp. 1 - 5, April, 2019,
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R. M. Martins, N. Lourenço, N. Horta, J. Y. Yin, P. M. Mak, R. P. M. Martins, Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow- Phase-Noise Cellular Applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 1, pp. 69 - 82, January, 2019,
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J. Carapuço, R. Neves, N. Horta, Reinforcement learning applied to Forex trading, Applied Soft Computing Journal, Vol. 73, No. 1, pp. 783 - 794, December, 2018 | BibTex
S. Sabino, N. Horta, A. Grilo, Centralized Unmanned Aerial Vehicle Mesh Network Placement Scheme: A Multi-Objective Evolutionary Algorithm Approach, Biosensors and Bioelectronics, Vol. 18, No. 12, pp. 4387 - 4387, December, 2018 | BibTex
A. Canelas, R. P. Póvoa, R. M. Martins, N. Lourenço, J.G. Guilherme, J.P.C Carvalho, N. Horta, FUZYE: A Fuzzy C-Means Analog IC Yield Optimization using Evolutionary-based Algorithms, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. n/a, No. n/a, pp. 1 - 13, November, 2018,
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F. Passos, R. M. Martins, N. Lourenço, E. Roca, R. P. Póvoa, A. Canelas, R. C.-L. Castro-López, N. Horta, F. V. F, Fernández, Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology, Integration, the VLSI Journal, Vol. 63, No. n/a, pp. 351 - 361, September, 2018,
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S. Mostafaa, N. Horta, A. Ravelo-García, F. Morgado-Dias, Analog active filter design using a multi objective genetic algorithm, AEU - International Journal of Electronics and Communications, Vol. 93, No., pp. 83 - 94, September, 2018,
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J. Baúto, A. Canelas, R. Neves, N. Horta, Parallel SAX/GA for financial pattern matching using NVIDIA’s GPU, Expert Systems with Applications, Vol. 105, No. n/a, pp. 77 - 88, September, 2018,
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J.G. Guilherme, J. Calvillo, R. P. Póvoa, N. Horta, Second-order compensation BGR with low TC and high performance for space applications, Integration, the VLSI Journal, Vol. 1, No. 1, pp. 1 - 10, July, 2018,
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R. M. Martins, N. Lourenço, F. Passos, R. P. Póvoa, A. Canelas, E. Roca, R. Castro-López, J. S. Sieiro, F. Fernández, N. Horta, Two-Step RF IC Block Synthesis with Pre-Optimized Inductors and Full Layout Generation In-the-loop, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. Early Access, No. Early Access, pp. Early Access - Early Access, May, 2018,
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B. Almeida, R. Neves, N. Horta, Combining Support Vector Machine with Genetic Algorithms to optimize investments in Forex markets with high leverage, Applied Soft Computing Journal, Vol. 64, No. 1, pp. 596 - 613, March, 2018 | BibTex
R. P. Póvoa, N. Lourenço, R. M. Martins, A. Canelas, N. Horta, JG Goes, Single Stage OTA biased by Voltage-Combiners with Enhanced Performance using Current Starving, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 1, No. 1, pp. 1 - 5, November, 2017,
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R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Stochastic-based placement template generator for analog IC layout-aware synthesis, Integration, the VLSI Journal, Vol. 58, No. n/a, pp. 485 - 495, June, 2017,
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M. Daniel, R. Neves, N. Horta, Company Event Popularity for Financial Markets Using Twitter and Sentiment Analysis, Expert Systems with Applications, Vol. 71, No. 0, pp. 111 - 124, April, 2017 | BibTex
R. P. Póvoa, N. Lourenço, R. M. Martins, A. Canelas, N. Horta, J. Goes, Single-Stage Amplifier biased by Voltage-Combiners with Gain and Energy-Efficiency Enhancement, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. PP, No. 99, pp. 1 - 1, March, 2017,
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J. Leitão, R. Neves, N. Horta, Combining Rules between PIPs and SAX to Identify Patterns in Financial Markets, Expert Systems with Applications, Vol. 65, No. 0, pp. 242 - 254, December, 2016 | BibTex
N. Lourenço, R. M. Martins, A. Canelas, R. P. Póvoa, N. Horta, AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation, Integration, the VLSI Journal, Vol. 55, No. 09, pp. 316 - 329, September, 2016,
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M. Pandey, A. Canelas, R. P. Póvoa, J. Torres, J. Costa Freire, N. Lourenço, N. Horta, Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer, Integration, the VLSI Journal, Vol., No., pp. -, September, 2016 | BibTex
D. Yazdani, A. Moghaddam, A. Dehban, N. Horta, A Novel Approach for Optimization in Dynamic Environments Based on Modified Artificial Fish Swarm Algorithm, International Journal of Computational Intelligence and Applications, Vol. 15, No. 2, pp. 1 - 16, June, 2016,
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R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Current-flow & Current-Density-aware Multi-Objective Optimization of Analog IC Placement, Integration, the VLSI Journal, Vol. --, No. --, pp. -- - --, June, 2016,
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N Neves, N. Horta, R. Neves, P Tomás, N Roma, Multi-Objective Kernel Mapping and Scheduling for Morphable Many-Core Architectures, Expert Systems with Applications, Vol. 45, No. 1, pp. 385 - 399, March, 2016,
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M. Mauro, N. Horta, J.G. Guilherme, Logarithmic AD Converter with Selectable Transfer Characteristic, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 63, No. 3, pp. 234 - 238, March, 2016,
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R. M. Martins, N. Lourenço, N. Horta, Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates, Expert Systems with Applications, Vol. 42, No. 23, pp. 9137 - 9151, December, 2015,
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J. Pinto, R. Neves, N. Horta, Boosting Trading Strategies Performance using VIX Indicator Together with a Dual-Objective Evolutionary Computation Optimizer, Expert Systems with Applications, Vol. 42, No. 19, pp. 6699 - 6716, November, 2015,
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M. Fotouhi Ghazvini, J. Soares, N. Horta, R. Neves, R. Castro, Z. Vale, A multi-objective model for scheduling of short-term incentive-based demand response programs offered by electricity retailers, Applied Energy, Vol. 151, No. 1, pp. 102 - 118, August, 2015,
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R. P. Póvoa, I. Bastos Bastos, N. Lourenço, N. Horta, Automatic Synthesis of RF Front-End Blocks Using Multi-Objective Evolutionary Techniques, Integration, the VLSI Journal, Vol. in press, No. in press, pp. in press - in press, July, 2015,
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N. Magaia, N. Horta, R. Neves, P. Pereira, M. Correia, A multi-objective routing algorithm for Wireless Multimedia Sensor Networks, Applied Soft Computing Journal, Vol. 30, No. 1, pp. 104 - 112, May, 2015,
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A. Silva Silva, R. Neves, N. Horta, A Hybrid Approach to Portfolio Composition based on Fundamental and Technical Indicators”, Expert Systems with Applications, Vol. 42, No. 4, pp. 2036 - 2048, March, 2015,
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N. Lourenço, A. Canelas, R. P. Póvoa, R. M. Martins, N. Horta, Floorplan-aware analog IC sizing and optimization based on topological constraints, Integration, the VLSI Journal, Vol. 48, No. 1, pp. 183 - 197, January, 2015,
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R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Electromigration-aware analog Router with multilayer multiport terminal structures, Integration, the VLSI Journal, Vol. 47, No. 4, pp. 532 - 547, September, 2014,
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M. Mauro, N. Horta, J.G. Guilherme, A survey on nonlinear analog-to-digital converters, Integration, the VLSI Journal, Vol. 47, No. 1, pp. 12 - 22, January, 2014,
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R. M. Martins, N. Lourenço, N. Horta, LAYGEN II—Automatic Layout Generation of Analog Integrated Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 11, pp. 1641 - 1654, November, 2013,
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R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Routing analog ICs using a multi-objective multi-constraint evolutionary approach, Analog Integrated Circuits and Signal Processing, Vol. 78, No. 1, pp. 123 - 135, June, 2013,
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A. Canelas, R. Neves, N. Horta, A SAX-GA Approach to Evolve Investment Strategies on Financial Markets based on Pattern Discovery Techniques, Expert Systems with Applications, Vol., No., pp. -, January, 2013,
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DG Guilherme, J.G. Guilherme, N. Horta, Automatic Topology Selection and Sizing of Class-D Loop-Filters for Minimizing Distortion Based on an Evolutionary Optimization Kernel, Analog Integrated Circuits and Signal Processing, Vol. 73, No. 10.1007/s10470-011-9716-4, pp. 21 - 32, October, 2012,
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A. Gorgulho Gorgulho, R. Neves, N. Horta, Applying a GA kernel on optimizing technical analysis rules for stock picking and portfolio composition, Expert Systems with Applications, Vol. 38, No. 11, pp. 14072 - 14085, October, 2011,
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R. Gama, J. Goes, R. Neves, N. Horta, Low-Power Open Loop Multiply-by-two Amplifier with Gain-accuracy Improved by Local-Feedback, Intrnl. Journal of Microelectronics and Computer Science, Vol. 1, No. 1, pp. 19 - 24, June, 2010 | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, Analog Circuits Optimization based on Evolutionary Computation Techniques, Integration, the VLSI Journal, Vol. 43, No. 1, pp. 136 - 155, January, 2010,
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A. Silva, J.G. Guilherme, N. Horta, Reconfigurable multi-mode sigma–delta modulator for 4G mobile terminals, Integration, the VLSI Journal, Vol. 42, No. 1, pp. 34 - 46, January, 2009,
| Abstract | Full text (PDF 1 MB) | BibTex
N. Horta, Analogue and Mixed-Signal Systems Topologies Exploration using Symbolic Methods, Analog Integrated Circuits and Signal Processing, Vol. 31, No. 2, pp. -, February, 2002 | BibTex
N. Horta, J.E. Franca, Algorithm-Driven Synthesis of Data Conversion Architectures, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 10, pp. 1116 - 1135, October, 1997 | BibTex

136Papers in Conferences

J. Domingues Domingues, A. Gusmão, N. Horta, N. Lourenço, R. M. Martins, Accelerating Voltage-Controlled Oscillator Sizing Optimizations with ANN-based Convergence Classifiers and Frequency Guess Predictors, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Sardinia, Italy, Vol., pp. -, June, 2022,
| Abstract | Full text (PDF 784 KBs) | BibTex
F. Passos, N. Lourenço, R. M. Martins, E. Roca, R. Castro-López, N. Horta, F. V. Fernandez Fernandez, Machine Learning Approaches for Transformer Modeling, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Villasimius, Italy, June, 2022 | Full text (PDF 1 MB) | BibTex
R. Vieira, F. Passos, R. P. Póvoa, R. M. Martins, N. Horta, J.G. Guilherme, N. Lourenço, Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD SMACD, Sardinia, Italy, Vol., pp. -, June, 2022,
| Abstract | Full text (PDF 971 KBs) | BibTex
Alves P. Alves, A. Gusmão, N. Horta, N. Lourenço, R. M. Martins, ANN-based Analog IC Floorplan Recommender with a Broader Topological Constraints Coverage, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Sardinia, Italy, Vol., pp. -, June, 2022,
| Abstract | Full text (PDF 898 KBs) | BibTex
N. Lourenço, F. Passos, R. Vieira, R. M. Martins, N. Horta, J.G. Guilherme, R. P. Póvoa, Radiation-Hardened Bandgap Voltage and Current Reference for Space Applications with 2.38 ppm/ºC Temperature Coefficient, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Villasimius, Italy, Vol., pp. -, June, 2022,
| Abstract | Full text (PDF 458 KBs) | BibTex
R. Vieira, F. Passos, A. Canelas, R. P. Póvoa, N. Lourenço, N. Horta, J.G. Guilherme, A Radiation-Hardened Frequency-Locked Loop On-Chip Oscillator with 33.6ppm/ºC Stability for Space Applications, IEEE International Symp. on Circuits and Systems - ISCAS, Austin Texas, United States, May, 2022,
| Abstract | Full text (PDF 775 KBs) | BibTex
A. Gusmão, N. Horta, N. Lourenço, R. M. Martins, Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement, ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, United States, December, 2021,
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R. Vieira, R. M. Martins, N. Horta, N. Lourenço, R. P. Póvoa, A Sub-1µA Low-Power Low-Noise Amplifier with Tunable Gain and Bandwidth for EMG and EOG Biopotential Signals, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Erfurt, Germany, July, 2021,
| Abstract | Full text (PDF 723 KBs) | BibTex
R. M. Martins, A. Gusmão, A. Canelas, F. Passos, N. Lourenço, N. Horta, An Essay on the Next Generation of Performance-driven Analog/RF IC EDA Tools: The Role of Simulation-based Layout Optimization, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Erfurt, Germany, July, 2021,
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A. Gusmão, A. Canelas, N. Horta, N. Lourenço, R. M. Martins, A Deep Learning Toolbox for Analog Integrated Circuit Placement, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Conference online, July, 2021,
| Abstract | BibTex
A. Gusmão, N. Lourenço, R. M. Martins, N. Horta, Bringing Structure into Analog IC Placement with Relational Graph Convolutional Networks, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Conference online, July, 2021,
| Abstract | BibTex
J.G. Guilherme, R. P. Póvoa, N. Lourenço, N. Horta, PROMISE, PROgrammable MIxed Signal ASIC Electronics Framework, ESA International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications AMICSA, Amsterdam, Netherlands, May, 2021,
| Abstract | BibTex
A. Gusmão, N. Lourenço, R. M. Martins, N. Horta, F. Passos, R. P. Póvoa, Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender, IEEE International Symposium on Circuits and Systems ISCAS, Sevilla, Spain, October, 2020,
| Abstract | BibTex
N. Lourenço, E. Moutaye, R. M. Martins, A. Canelas, R. P. Póvoa, N. Horta, Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019,
| Abstract | Full text (PDF 647 KBs) | BibTex
N. Lourenço, E. Afacan, R. M. Martins, F. Passos, A. Canelas, R. P. Póvoa, N. Horta, G. Dundar, Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019,
| Abstract | Full text (PDF 908 KBs) | BibTex
F. Passos, E. Roca, R. Castro-López, N. Horta, F. V. Fernandez Fernandez, Synthesis of mm-Wave circuits using-EM-simulated passive structure libraries, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019,
| Abstract | BibTex
R. P. Póvoa, R. M. Martins, N. Lourenço, A. Canelas, N. Horta, JG Goes, A LowNoise CMOS Inverter-Based OTA for Biomedical and Healthcare Signal Receivers, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019 | BibTex
D. Guerra, A. Canelas, R. P. Póvoa, N. Horta, N. Lourenço, R. M. Martins, Artificial Neural Networks as an Alternative for Automatic Analog IC Placement, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019,
| Abstract | BibTex
R. M. Martins, N. Lourenço, R. P. Póvoa, N. Horta, On the Exploration of Design Tradeoffs in Analog IC Placement with Layout-dependent Effects, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019,
| Abstract | BibTex
R. M. Martins, N. Lourenço, N. Horta, J. Y. Yin, P. M. Mak, R. P. M. Martins, Using EDA Tools to Push the Performance Boundaries of an Ultralow-Power IoT-VCO at 65nm, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, July, 2019,
| Abstract | BibTex
J. Z. Zangpo, J.G. Guilherme, N. Horta, A 302 uW CMOS Temperature Sensor to compensate frequency drift for an oscillator, IEEE Annual Information Technology, Electronics and Mobile Communication Conference IEMECON, Jaipur, India, Vol. 1, pp. 1 - 4, March, 2019,
| Abstract | Full text (PDF 377 KBs) | BibTex
J.G. Guilherme, J. Z. Zangpo, R. P. Póvoa, N. Horta, An Integrated LC Oscillator with Self Compensation for Frequency Drift and PVT Corners Variations, IEEE International Conf. on Electronics, Circuits and Integrated Systems - ICECS, Bordeaux, France, Vol. 1, pp. 333 - 336, December, 2018,
| Abstract | Full text (PDF 1 MB) | BibTex
N. Lourenço, J. Rosa, R. M. Martins, H. Aidos, A. Canelas, R. P. Póvoa, N. Horta, On the Exploration of Promising Analog IC Designs via Artificial Neural Networks, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, Vol., pp. 133 - 136, July, 2018,
| Abstract | BibTex
J.G. Guilherme, R. Granja, M. Mauro, N. Horta, 11.7b Time-To-Digital Converter with 0.82ps resolution in 130nm CMOS Technology, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Prague, Czech Republic, July, 2018,
| Abstract | BibTex
J.G. Guilherme, A. Canelas, R. P. Póvoa, N. Lourenço, N. Horta, A 20 dB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, July, 2018,
| Abstract | BibTex
F. Passos, E. Roca, R. Castro-López, F. Fernández, R. P. Póvoa, R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, July, 2018 | BibTex
R. M. Martins, N. Lourenço, N. Horta, J. Y. Yin, P. M. Mak, R. P. M. Martins, Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, July, 2018,
| Abstract | BibTex
T. Pessoa, N. Lourenço, R. M. Martins, R. P. Póvoa, N. Horta, Enhanced Analog and RF IC Sizing Methodology using PCA and NSGA-II Optimization Kernel, Design, Automation, and Test in Europe - DATE, Dresden, Germany, Vol., pp. 1 - 4, March, 2018,
| Abstract | Full text (PDF 1 MB) | BibTex
J. Calvillo, J.G. Guilherme, N. Horta, Design of a BGR suitable for The Space Industry with Performance of 1.25 V with 0.758 ppm/°C TC from - 55° to 125°C, New Generation of Circuits and Systems NGCAS, Genova, Italy, September, 2017,
| Abstract | Full text (PDF 1 MB) | BibTex
C. V. S. Simões, R. Neves, N. Horta, Using Sentiment from Twitter optimized by Genetic Algorithms to Predict the Stock Market, IEEE Congress on Evolutionary Computation - CEC, San Sabastian, Spain, Vol. 1, pp. 1 - 8, June, 2017 | BibTex
R. M. Martins, N. Lourenço, R. P. Póvoa, A. Canelas, N. Horta, F. Passos, R. Castro-López, E. Roca, F. Fernández, Layout-Aware Challenges and a Solution for the Automatic Synthesis of Radio-Frequency IC Blocks, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Taormina, Italy, June, 2017,
| Abstract | BibTex
R. P. Póvoa, A. Canelas, R. M. Martins, N. Lourenço, N. Horta, JG Goes, Dynamic Voltage-Combiners Biased OTA for Low-Power High-Speed SC Circuits, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Taormina, Italy, June, 2017 | BibTex
N. Lourenço, R. M. Martins, R. P. Póvoa, A. Canelas, N. Horta, F. Passos, R. Castro-López, E. Roca, F. Fernández, New Mapping Strategies for Pre-Optimized Inductor Sets in Bottom-Up RF IC Sizing Optimization, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Taormina, Italy, June, 2017,
| Abstract | BibTex
F. Passos, R. C.-L. Castro-López, E. Roca, F. V. F, Fernández, R. M. Martins, N. Lourenço, R. P. Póvoa, A. Canelas, N. Horta, Systematic Design of a Voltage Controlled Oscillator using a Layout-Aware Approach, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Taormina, Italy, June, 2017,
| Abstract | BibTex
A. Canelas, R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Efficient Yield Optimization Method using a Variable K-Means Algorithm for Analog IC Sizing, Design, Automation, and Test in Europe - DATE, Lausanne, Switzerland, Vol. N/A, pp. 1 - 6, March, 2017,
| Abstract | BibTex
J. Cachaço, N. Machado, N. Lourenço, J.G. Guilherme, N. Horta, Automatic Technology Migration of Analog IC Designs using Generic Cell Libraries, Design, Automation, and Test in Europe - DATE, Lausanne, Switzerland, Vol. N/A, pp. 1 - 4, March, 2017,
| Abstract | BibTex
A. Ferreira, N. Lourenço, R. M. Martins, N. Horta, Automated analog IC design constraints generation for a layout-aware sizing approach, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lisboa, Portugal, Vol. --, pp. 1 - 4, June, 2016,
| Abstract | BibTex
A. Fitas, J.G. Guilherme, N. Horta, Design of a radiation-hardened curvature compensated bandgap reference circuit, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Lisboa, Portugal, Vol. 1, pp. 1 - 4, June, 2016,
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C. Silva, J.G. Guilherme, N. Horta, SCALES: A high speed simulator tool for pipeline A/D converters, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lisbon, Portugal, Vol. 1, pp. 1 - 4, June, 2016,
| Abstract | BibTex
A. Canelas, R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Yield Optimization using K-Means Clustering Algorithm to reduce Monte Carlo Simulations, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lisbon, Portugal, Vol. n/a, pp. 1 - 4, June, 2016,
| Abstract | BibTex
R. M. Martins, A. Canelas, N. Lourenço, N. Horta, On-the-fly Exploration of Placement Templates for Analog IC Layout-aware Sizing Methodologies, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lisboa, Portugal, Vol. n/a, pp. 1 - 4, June, 2016 | BibTex
M. Mauro, N. Horta, J.G. Guilherme, An 8bit Logarithmic AD Converter Using Cross- Coupled Inverters and a Time-to-Digital Converter, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Lisbon, Portugal, Vol., pp. 1 - 4, June, 2016,
| Abstract | BibTex
D. Neves, R. M. Martins, N. Lourenço, N. Horta, Design Automation Tasks Scheduling for Enhanced Parallel Execution of a State-of-the-Art Layout-Aware Sizing Approach, Design, Automation, and Test in Europe - DATE, Dresden, Germany, Vol. n/a, pp. 1 - 4, March, 2016,
| Abstract | BibTex
R. M. Martins, N. Lourenço, N. Horta, M. Santos, Embedding Fault List Compression Techniques in a Design Automation Framework for Analog and Mixed-Signal Structural Testing, Conference on Design of Circuits and Integrated Systems DCIS, Estoril, Portugal, Vol. n/a, pp. n/a - n/a, November, 2015,
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R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Exploring Design Tradeoffs in Analog IC Placement with Current-Flow & Current-Density Considerations, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. n/a, pp. n/a - n/a, September, 2015,
| Abstract | BibTex
R. M. Martins, N. Lourenço, A. Canelas, R. P. Póvoa, N. Horta, AIDA: Robust Layout-Aware Synthesis of Analog ICs including Sizing and Layout Generation, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. n/a, pp. n/a - n/a, September, 2015,
| Abstract | BibTex
D. Neves, N. Lourenço, N. Horta, Scheduling evaluation tasks for increased efficiency of parallel analog IC synthesis, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. na, pp. 1 - 4, September, 2015,
| Abstract | BibTex
M. Pandey, A. Canelas, R. P. Póvoa, J. Torres, J. Costa Freire, N. Lourenço, N. Horta, Grounded Active Inductors Design Optimization for FQmax = 14.2 GHz using a 130 nm CMOS Technology, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. -, pp. 1 - 4, September, 2015 | BibTex
J.M. Machado, R. Neves, N. Horta, Developing Multi-Time Frame Trading Rules with a Trend Following Strategy, using GA, Genetic and Evolutionary Computation Conf. - GECCO, madrid, Spain, Vol. 1, pp. 765 - 766, July, 2015,
| Abstract | BibTex
R. M. Martins, N. Lourenço, N. Horta, Analog IC Placement using Absolute Coordinates and a Hierarchical Combination of Pareto Optimal Fronts, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Glasgow, United Kingdom, June, 2015,
| Abstract | BibTex
B. Cardoso, R. M. Martins, N. Lourenço, N. Horta, AIDA-PEx: Accurate Parasitic Extraction for Layout-Aware Analog Integrated Circuit Sizing, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Glasgow, United Kingdom, June, 2015,
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R. P. Póvoa, N. Lourenço, N. Horta, J. Goes, A Voltage-Combiners-Biased Amplifier with Enhanced Gain and Speed using Current Starving, IEEE International Symp. on Circuits and Systems - ISCAS, Lisboa, Portugal, May, 2015 | Full text (PDF 418 KBs) | BibTex
R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Extraction and Application of Wiring Symmetry Rules to Route Analog Multiport Terminals, IEEE International Symp. on Circuits and Systems - ISCAS, Lisboa, Portugal, Vol. n/a, pp. 1945 - 1948, May, 2015,
| Abstract | BibTex
J.G. Guilherme, N. Horta, Thermal-aware floorplanning and layout generation of MOSFET power stages, IEEE International Symp. on Circuits and Systems - ISCAS, Lisbon, Portugal, Vol. 1, pp. 1 - 4, May, 2015,
| Abstract | BibTex
N. Lourenço, R. M. Martins, N. Horta, Layout-Aware Sizing of Analog ICs using Floorplan & Routing Estimates for Parasitic Extraction, Design, Automation and Test in Europe Conf., Grenoble, France, Vol. 0, pp. 1 - 6, March, 2015,
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R. P. Póvoa, N. Lourenço, N. Horta, RST Santos Tavares, J. Goes, A Cascode-Free Single-Stage Amplifier using a Fully-Differential Folded Voltage-Combiner, IEEE International Conf. on Electronics, Circuits and Systems, Marselha, France, December, 2014 | BibTex
B. Silva, J.G. Guilherme, N. Horta, A Rad-Hard DC-DC Converter Controller, IEEE International Conf. on Electronics, Circuits and Integrated Systems - ICECS, Marseille, France, Vol. 1, pp. 439 - 442, December, 2014,
| Abstract | BibTex
J.G. Guilherme, N. Horta, Automatic Layout Generation of Power MOSFET Transistors in Bulk CMOS, IEEE International Conf. on Electronics, Circuits and Integrated Systems - ICECS, marseille, France, Vol. 1, pp. 606 - 609, December, 2014,
| Abstract | BibTex
M. Mauro, N. Horta, J.G. Guilherme, Logarithmic AD Conversion Using Latched Comparators and a Time-to-Digital Converter, IEEE International Conf. on Electronics, Circuits and Integrated Systems - ICECS, Marseille, France, Vol., pp. 319 - 322, December, 2014,
| Abstract | BibTex
R. P. Póvoa, R. Lourenço Lourenço, N. Lourenço, A. Canelas, R. M. Martins, N. Horta, LC-VCO Automatic Synthesis Using Multi-Objective Evolutionary Techniques, IEEE International Symp. on Circuits and Systems - ISCAS, Melbourne, Australia, June, 2014 | BibTex
J. Pinto, R. Neves, N. Horta, Multi-Objective Optimization of Investment Strategies Based on Evolutionary Computation Techniques, in Volatile Environments, International Conf. on Enterprise Information Systems, ICEIS, Lisboa, Portugal, Vol. NA, pp. 480 - 488, April, 2014,
| Abstract | Full text (PDF 707 KBs) | BibTex
A. V. Silva Silva, R. Neves, N. Horta, Portfolio Optimization Using Fundamental Indicators Based on Multi-Objective EA, IEEE Computational Intelligence for Financial Engineering and Economics - CIFEr, London, United Kingdom, Vol. I, pp. 1 - 4, March, 2014 | BibTex
R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures, Design, Automation, and Test in Europe - DATE, Dresden, Germany, Vol. n/a, pp. 1 - 6, March, 2014,
| Abstract | BibTex
R. P. Póvoa, N. Lourenço, N. Horta, RST Santos Tavares, J. Gomes, Single-Stage Amplifiers with Gain Enhancement and Improved Energy-Efficiency employing Voltage-Combiners, IFIP/IEEE International Conf. on Very Large Scale Integration, Istambul, Turkey, October, 2013,
| Abstract | BibTex
A. Canelas, R. Neves, N. Horta, Multi-Dimensional Pattern Discovery in Financial Time Series using SAX-GA with extended robustness, Genetic and Evolutionary Computation Conf. - GECCO, Amsterdam, Netherlands, Vol. 0, pp. 1 - 3, July, 2013,
| Abstract | BibTex
R. Neves, N. Horta, Optimizing Investment Strategies based on Companies Earnings using Genetic Algorithms, Genetic and Evolutionary Computation Conf. - GECCO, Amsterdam, Netherlands, Vol. 0, pp. 1 - 3, July, 2013,
| Abstract | BibTex
F.C. Cadete, N. Lourenço, M.B. Barros, R. M. Martins, N. Horta, A New Metaheuristc Combining Gradient Models with NSGA-II to Enhance Analog IC Synthesis, IEEE Congress on Evolutionary Computation - CEC, Cancun, Mexico, June, 2013,
| Abstract | BibTex
R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Multi-Port Multi-Terminal Analog Router based on an Evolutionary Optimization Kernel, IEEE Congress on Evolutionary Computation - CEC, Cancún, Mexico, Vol. n/a, pp. 2789 - 2796, June, 2013,
| Abstract | BibTex
F. Rocha, R. P. Póvoa, N. Lourenço, R. M. Martins, N. Horta, A New Metaheuristc Combining Gradient Models with NSGA-II to Enhance Analog IC Synthesis, IEEE Congress on Evolutionary Computation - CEC, Cancún, Mexico, June, 2013 | BibTex
F.C. Cadete, R. M. Martins, N. Lourenço, N. Horta, Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel, Doctoral Conf. on Computing, Electrical and Industrial Systems - DOCEIS, Lisbon, Portugal, April, 2013,
| Abstract | BibTex
N. Leite Leite, R. Neves, N. Horta, F. Melício Melício, A.C.R. Rosa, Solving an Uncapacitated Exam Timetabling Problem Instance using a Hybrid NSGA-II, International Conf. on Evolutionary Computation Theory and Applications - ECTA, Barcelona, Spain, October, 2012 | BibTex
J.G. Guilherme, C. Silva, N. Horta, SCALES – A Behavioral Simulator for Pipelined Analog-to-Digital Converter Design, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Seville, Spain, Vol. 1, pp. 149 - 152, September, 2012,
| Abstract | BibTex
R. M. Martins, N. Lourenço, N. Horta, Multi-Objective Multi-Constraint Routing of Analog ICs using a Modified NSGA-II Approach, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Seville, Spain, Vol. n/a, pp. 65 - 68, September, 2012,
| Abstract | BibTex
R. M. Martins, N. Lourenço, J.G. Guilherme, N. Horta, AIDA: Automated Analog IC Design Flow from Circuit Level to Layout, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Seville, Spain, Vol. n/a, pp. 29 - 32, September, 2012,
| Abstract | BibTex
O. Y. Yefimochkin, R. Neves, N. Horta, An Evolutionary Approach to Define Investment Strategies based on Macroeconomic Indicators and VIX Data, Genetic and Evolutionary Computation Conf. - GECCO, Philadelphia, United States, July, 2012,
| Abstract | BibTex
A. Canelas, R. Neves, N. Horta, A New SAX-GA Methodology applied to Investment Strategies Optimization, Genetic and Evolutionary Computation Conf. - GECCO, Philadelphia, United States, July, 2012,
| Abstract | BibTex
J. Pinto, N. Horta, Automated Passive Filter Design Using Multi-objective Genetic Algorithms with Variable Parameters, Genetic and Evolutionary Computation Conf. - GECCO, Philadelphia, United States, Vol. NA, pp. NA - NA, July, 2012,
| Abstract | Full text (PDF 356 KBs) | BibTex
N. Lourenço, N. Horta, GENOM-POF: Multi-Objective Evolutionary Synthesis of Analog ICs with Corners Validation, Genetic and Evolutionary Computation Conf. - GECCO, Philadelphia, United States, Vol., pp. 1119 - 1126, July, 2012,
| Abstract | BibTex
R. M. Martins, N. Lourenço, N. Horta, LAYGEN II – Automatic Analog ICs Layout Generator based on a Template Approach, Genetic and Evolutionary Computation Conf. - GECCO, Philadelphia, United States, Vol. n/a, pp. 1127 - 1134, July, 2012,
| Abstract | BibTex
F.C. Cadete, DG Guilherme, J.G. Guilherme, N. Horta, F.C. Cadete, Overcurrent Detection Circuit for Integrated Class-D Amplifiers, European Conf. on Circuit Theory and Design, Linköping, Sweden, Vol. 1, pp. 410 - 413, September, 2011,
| Abstract | BibTex
P. Sousa, C. Duarte, M.B. Barros, J.G. Guilherme, N. Horta, Optimal OpAmp Sizing based on a Fuzzy-Genetic Kernel, Genetic and Evolutionary Computation Conf. - GECCO, Dublin, Ireland, July, 2011,
| Abstract | Full text (PDF 331 KBs) | BibTex
J. Pinto, R. Neves, N. Horta, Fitness Function Evaluation for MA Trading Strategies based on Genetic Algorithms, Genetic and Evolutionary Computation Conf. - GECCO, Dublin, Ireland, Vol. NA, pp. 819 - 820, July, 2011,
| Abstract | Full text (PDF 419 KBs) | BibTex
P. Parracho Parracho, R. Neves, N. Horta, Trading with Optimized Uptrend and Downtrend Pattern Templates using a Genetic Algorithm Kernel, IEEE Congress on Evolutionary Computation - CEC, New Orleans, United States, June, 2011,
| Abstract | Full text (PDF 541 KBs) | BibTex
A. Simões, R. Neves, N. Horta, An Innovative GA Optimized Investment Strategy based on a New Technical Indicator using Multiple MAs, IJCCI International Conf. on Evolutionay Computation - ICEC, Valencia, Spain, Vol. 1, pp. 1 - 4, October, 2010,
| Abstract | Full text (PDF 149 KBs) | BibTex
DG Guilherme, J.G. Guilherme, N. Horta, Automatic Topology Selection and Sizing of Class-D Loop-Filters for Minimizing Distortion, International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design - SM2ACD, Gammarth, Tunisia, Vol. 1, pp. 1 - 4, October, 2010,
| Abstract | BibTex
DG Guilherme, J.G. Guilherme, N. Horta, An Automated Design Methodology for Audio Class-D Loop-Filters Optimized for THD+N, International Analog VLSI Workshop - AVLSIWS, Pavia, Italy, Vol. 1, pp. 47 - 51, September, 2010,
| Abstract | Full text (PDF 404 KBs) | BibTex
P. Parracho Parracho, R. Neves, N. Horta, Trading in Financial Markets using Pattern Recognition Optimized by Genetic Algorithms, Genetic and Evolutionary Computation Conf. - GECCO, Portland, United States, Vol. 1, pp. 1 - 1, July, 2010 | Full text (PDF 268 KBs) | BibTex
P. Sousa, C. Duarte, J.G. Guilherme, N. Horta, Enhancing Analog IC Design Optimization Kernels with Simple Fuzzy Models, European Conf. on Circuit Theory and Design, Antalya, Turkey, August, 2009,
| Abstract | Full text (PDF 340 KBs) | BibTex
P. Sousa, C. Duarte, N. Horta, FUGA: A Fuzzy-Genetic Analog Circuit Optimization, Genetic and Evolutionary Computation Conf. - GECCO, Montreal, Canada, July, 2009,
| Abstract | Full text (PDF 194 KBs) | BibTex
A. Gorgulho Gorgulho, R. Neves, N. Horta, Using GAs to Balance Technical Indicators on Stock, Genetic and Evolutionary Computation Conf. - GECCO, Montreal, Canada, July, 2009,
| Abstract | BibTex
R. Gama, R. Neves, N. Horta, Design of a low-power, open loop, multiply-by-two amplifier with gain-accuracy improved by local-feedback, International Conf. Mixed Design of Integrated Circuits and Systems - MIXDES, Lodz, Poland, Vol. 1, pp. 1 - 5, June, 2009 | Full text (PDF 162 KBs) | BibTex
A. Ribeiro, T. Costa, R. Gama, R. Neves, N. Horta, A bandgap Voltage Reference with Only CMOS Transistors, Conf. on Telecommunications - ConfTele, Santa maria da Feira, Portugal, Vol. I, pp. 69 - 72, May, 2009 | Full text (PDF 125 KBs) | BibTex
T. Costa, R. Neves, N. Horta, Low-Area 4th-Order Shared-Amplfier Sigms-delta Modulator, Conf. on Telecommunications - ConfTele, Santa maria da Feira, Portugal, Vol. I, pp. 65 - 68, May, 2009 | Full text (PDF 192 KBs) | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, Analog Circuits Optimization based on Evolutionary Computation Techniques, Conf. on Telecommunications - ConfTele, Feira, Portugal, Vol. 1, pp. 1 - 1, April, 2009,
| Abstract | BibTex
M. Mauro, C. Pires, J.G. Guilherme, N. Horta, Overview of Radiation Effects and Design Constraints off Fully Custom SMPS, IEEE Asia Pacific Conf. on Circuits and Systems - APCCAS, Macau, China, Vol. 1, pp. 372 - 375, December, 2008,
| Abstract | BibTex
P. Sousa, C. Duarte, N. Horta, Enhancing a GA Optimization Kernel based on Fuzzy Design Rules, International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design - SM2ACD, Erfurt, Germany, October, 2008,
| Abstract | Full text (PDF 524 KBs) | BibTex
N. Horta, M.B. Barros, J.G. Guilherme, Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques, International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design - SM2ACD, Erfurt, Germany, October, 2008,
| Abstract | Full text (PDF 776 KBs) | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques, International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design - SM2ACD, Erfurt, Germany, Vol., pp. 68 - 73, October, 2008,
| Abstract | BibTex
M. Figueira, J.G. Guilherme, N. Horta, Radiation Hardened SMPS, International Workshop on Analog and Mixed-Signal Integrated Circuits for Space Applications - AMICSA, Sintra, Portugal, September, 2008 | BibTex
M. Mauro, C. Pires, J.G. Guilherme, N. Horta, Radiation Hardened SMPS, Power Converter and Integrated Circuit Design Controller, International Workshop on Analog and Mixed-Signal Integrated Circuits for Space Applications - AMICSA, Cascais, Portugal, Vol. 1, pp. 1 - 8, August, 2008,
| Abstract | BibTex
N. Horta, A. Silva, J.G. Guilherme, A Reconfigurable A/D Converter for 4G Wireless, IEEE International Symp. on Circuits and Systems - ISCAS, Seattle, United States, Vol., pp. 924 - 927, May, 2008,
| Abstract | BibTex
N. Horta, A. Silva, J.G. Guilherme, Design of a Multimode Reconfigurable Sigma-Delta Converter for 4G Wireless Receivers, European Conf. on Circuit Theory and Design, , Spain, August, 2007 | BibTex
N. Horta, M.B. Barros, J.G. Guilherme, An Evolutionary Optimization Kernel Using a Dynamic GA-SVM Model Applied to Analog IC Design, European Conf. on Circuit Theory and Design, , Spain, August, 2007 | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, An Evolutionary Optimization Kernel Using a Dynamic GA-SVM Model Applied to Analog IC Design, European Conf. on Circuit Theory and Design, Seville, Spain, Vol., pp. 33 - 35, August, 2007 | BibTex
R. Neves, J.G. Guilherme, N. Horta, Designing Reconfigurable Multi-Standard Analog Baseband Front-End for 4G Mobile Terminals: System Level Design, Conf. on Telecommunications - ConfTele, Peniche, Portugal, Vol. I, pp. 1 - 4, May, 2007 | BibTex
N. Lourenço, N. Horta, LAYGEN - Automatic Analog ICs Layout Generator, Conf. on Telecommunications - ConfTele, Peniche, Portugal, Vol. 0, pp. 165 - 168, May, 2007,
| Abstract | BibTex
N. Horta, A. Charas, J. Morgado, PLASTIC: Automatic Characterization and Modeling of Organic Transistors for IC Design and Simulation, Conf. on Telecommunications - ConfTele, Peniche, Portugal, March, 2007 | BibTex
N. Horta, M.B. Barros, J.G. Guilherme, GA-SVM Feasibility Model and Optimization Kernel applied to Analog IC Design Automation, ACM Great Lakes VLSI - GLSVLSI), , Italy, March, 2007 | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, GA-SVM Feasibility Model and Optimization Kernel applied to Analog IC Design Automation, ACM Great Lakes VLSI - GLSVLSI), Stresa, Italy, Vol., pp. 469 - 472, March, 2007 | BibTex
N. Horta, G. Neves, M.B. Barros, AIDA: Analog IC Design Automation based on a Fully Configurable Design Hierarchy and Flow, IEEE International Conf. on Electronics, Circuits and Systems, , France, December, 2006 | BibTex
N. Horta, M.B. Barros, J.G. Guilherme, GA-SVM Optimization Kernel applied to Analog IC Design Automation, IEEE International Conf. on Electronics, Circuits and Systems, , France, December, 2006 | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, GA-SVM Optimization Kernel applied to Analog IC Design Automation, IEEE International Conf. on Electronics, Circuits and Integrated Systems - ICECS, Nice, France, Vol., pp. 486 - 489, December, 2006 | BibTex
N. Lourenço, M.V. Vianello, J.G. Guilherme, N. Horta, LAYGEN - Automatic Layout Generation of Analog ICs from Hierarchical Template Descriptions, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Otranto, Italy, Vol. 0, pp. 213 - 216, June, 2006,
| Abstract | BibTex
N. Lourenço, N. Horta, LAYGEN – An Evolutionary approach to automatic analog IC Layout Generation, IEEE Conf. on Electronics, Circuits and System, Gammarth, Tunisia, Vol. 1, pp. 1 - 2, December, 2005,
| Abstract | BibTex
N. Horta, G. Neves, Design Automation Methodology for Analog IC Design Matching Designers Approach, International Symp. on Signals, Circuits and Systems, Iasi, Romania, July, 2005 | BibTex
N. Horta, M.B. Barros, An Evolutionary Optimization Kernel with Adaptive Parameters applied to Analog Circuit Design, International Symp. on Signals, Circuits and Systems, Iasi, Romania, July, 2005 | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, An Evolutionary Optimization Kernel with Adaptive Parameters applied to Analog Circuit Design, International Symp. on Signals, Circuits and Systems, Iasi, Romania, Vol. 2, pp. 545 - 548, July, 2005 | BibTex
N. Horta, D. Simões, Evolving Standards in E-Learning: A Case-Study, Conf. on Telecommunications - ConfTele, Tomar, Portugal, April, 2005 | BibTex
N. Horta, M.B. Barros, An Evolutionary Optimization Approach applied to Analog Circuit Design, Conf. on Telecommunications - ConfTele, Tomar, Portugal, April, 2005 | BibTex
N. Horta, Analog and Mixed-Signal IC Design Automation: Synthesis and Optimization Overview, Conf. on Telecommunications - ConfTele, Tomar, Portugal, April, 2005 | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, An Evolutionary Optimization Approach applied to Analog Circuit Design, Conf. on Telecommunications - ConfTele, Tomar, Portugal, April, 2005 | BibTex
N. Horta, M.B. Barros, G. Neves, J.G. Guilherme, A Distributed Enhanced Genetic Algorithm Kernel Applied to a Circuit/Level Optimization EDesign Environment, Conf. on Design of Circuits and Integrated Systems, Bordeaux, France, November, 2004 | BibTex
M.B. Barros, G. Neves, J.G. Guilherme, N. Horta, A Distributed Enhanced Genetic Algorithm Kernel Applied to a Circuit/Level Optimization EDesign Environmen, Conf. on Design of Circuits and Integrated Systems, Bordeaux, France, Vol., pp. 20 - 24, November, 2004 | BibTex
N. Horta, R. Luis, D. Simões, A Multi-Level Model for Tracking Analysis in E-Learning Platforms, IEEE International Conf. on Advanced Learning Technologies, Helsinki, Finland, September, 2004 | BibTex
N. Horta, D. Simões, R. Luis, Enhancing the SCORM Modelling Scope, IEEE International Conf. on Advanced Learning Technologies, Helsinki, Finland, September, 2004 | BibTex
N. Horta, M.B. Barros, J. Silva, G. Neves, Enhanced Genetic Algorithm Kernel Applied to a Circuit-Level Optimization E-Design Environment, IEEE Conf. on Electronics, Circuits and System, Sharjah, United Arab Emirates, December, 2003 | BibTex
N. Horta, J. Redol, R. Luis, D. Simões, Data Warehousing and Data Mining Applied to an E-Learning Platform, International Conf. on Multimedia and ICTs in Education, Badajoz, Spain, December, 2003 | BibTex
M.B. Barros, J. Silva, G. Neves, J.G. Guilherme, N. Horta, Enhanced Genetic Algorithm Kernel Applied to a Circuit-Level Optimization E-Design Environment, IEEE Conf. on Electronics, Circuits and System, Sharjah, United Arab Emirates, Vol., pp. 1046 - 1049, December, 2003 | BibTex
N. Horta, D. Simões, R. Luis, J. Redol, A New Approach Towards E-Learning Contents Standardization And Enhanced Usability, IADIS International Conf. on WWW/Internet, Albufeira, Portugal, Vol. 1, pp. 1199 - 1103, November, 2003 | BibTex
N. Horta, J. Redol, D. Simões, VIANET-A New Web Framework for Distance Learning, IEEE International Conf. on Advanced Learning Technologies, Athens, Greece, July, 2003 | BibTex
R. Neves, N. Horta, Banner - Intelligent Management of Banner Advertisements on the WWW, International Conf. on Data Mining, Florence, Italy, Vol. 1, pp. 11 - 15, September, 2002 | BibTex
N. Horta, J. Iria, Towards a Framework for Semantic Service Discovery in Ubiquitous P2P Environment, International Conf. on Internet Computing, Las Vegas, United States, June, 2002 | BibTex
J. Silva, N. Horta, GENOM: Circuit-Level Optimizer Based on a Modified Genetic Algorithm Kernel, IEEE International Symp. on Circuits and Systems - ISCAS, Phoenix, Arizona, United States, May, 2002 | BibTex
J. Silva, N. Horta, E-Design Front-End for an IC optimizer based on a Genetic Algorithm, European Workshop on Microelectronics Education, Vigo, Spain, May, 2002 | BibTex
M. Fino, N. Horta, Symbolic Techniques Applied to Switched-Current ADCs Synthesis, IEEE International Symp. on Circuits and Systems - ISCAS, Geneve, Switzerland, Vol. 1, pp. 1124 - 1127, May, 2000 | BibTex
J.G. Guilherme, N. Horta, Symbolic Synthesis of Non-Linear Data Converters, IEEE International Conf. on Electronics, Circuits and Systems, Lisbon, Portugal, Vol. 3, pp. 219 - 222, September, 1998 | BibTex

Projects

Currently running projects2

Acronym	Name	Funding Agency	Start date	Ending date
PROMISE	PROgrammable MIxed Signal Electronics	EU/H2020	01-01-2020	31-12-2022
SYSTEMIC-RF	Automated synthesis methodology for reliable RF integrated circuits	EU/H2020	01-09-2021	31-08-2023

Closed Projects13

Acronym	Name	Funding Agency	Start date	Ending date
AIDA	AIDA – Automated P-Cell Generation based on Multi-Objective Optimization and Pareto Optimal Front Circuit Level Characterization	IT/LA	01-10-2011	01-12-2013
AIDA-C	AIDA-C: Analog IC Optimizer	Thales Alenia Space	01-10-2013	01-11-2021
AISMAD	AISMAD – Advanced Integrated Switched-Mode Audio Drivers	IT/LA	01-07-2011	01-12-2013
DISRUPTIVE	DISRUPTIVE - A Paradigm Shift in the Design of Analog and Mixed-Signal Nanoelectronic Circuits and Systems	FCT	01-04-2013	01-12-2016
EVOLUTION	Exploring Evolutionary Computation to Enhance Analog IC Design Automation Methodologies	FCT/POSC	01-08-2005	31-07-2007
HEAD	HEAD – Integrated Class D Audio Amplifier with High Efficiency	IT/LA	01-11-2008	01-11-2010
LAY(RF)^2	Ready-to-Fabricate RF and mmWave Integrated Circuit Layouts	IT	01-02-2020	31-01-2022
LAYGEN	Automatic Layout Generation of Mixed-Signal ICs	IT/LA	01-04-2006	31-03-2008
OPERA	OPERA - Layout-Aware Analog IC Design Automation	IT/LA	01-03-2014	01-02-2016
PLASTIC	Fully Patterned all Plastic Integrated Circuits	IT/LA	01-07-2005	01-09-2007
SCALES	SCALES - Simulation Tool for Pipeline ADCs	Thales Alenia Space	01-04-2011	01-04-2014
Space-DCDC	Space-DCDC – DC-DC controller for space applications	IT/LA	01-10-2008	01-10-2010
SPEED	Low Power Ultra-High Speed Analogue-to-Digital Converter for Ultra-Wideband Wireless Communications	FCT/PTDC	01-09-2007	01-03-2011

Other Scientific Achievements

11Awards

N. Lourenço, R. M. Martins, A. Canelas, R. P. Póvoa, N. Horta, Best Paper Award 2019 - Integration, the VLSI Journal, N. Lourenço, R. Martins, A. Canelas, R. Póvoa, and N. Horta, “AIDA: Layout-aware Analog Circuit-Level Sizing with In-Loop Layout Generation”, Integration, the VLSI Journal, 2016. DOI: 10.1016/j.vlsi.2016.04.009, 01-07-2019
D. Guerra, N. Lourenço, A. Canelas, R. P. Póvoa, N. Horta, R. M. Martins, Best Paper Award Runner-Up - International Conference on SMACD, Daniel Guerra, António Canelas, Ricardo Póvoa, Nuno Horta, Nuno Lourenço and Ricardo Martins "Artificial Neural Networks as an Alternative for Automatic Analog IC Placement", International Conference on SMACD 2019, Switzerland., 01-07-2019
F. Passos, R. M. Martins, N. Lourenço, E. Roca, R. Castro-López, A. Canelas, R. P. Póvoa, N. Horta, F. V. Fernandez Fernandez, Best Paper Award, Best paper award in SMACD 2018, 01-07-2018
J. Calvillo, J.G. Guilherme, N. Horta, Silver Leaf Award, Silver Leaf Award for Design of a BGR suitable for The Space Industry with Performance of 1.25 V with 0.758 ppm/°C TC from - 55° to 125°C in New Generation of Circuit and Systems Conference., 01-09-2017
R. M. Martins, A. Canelas, N. Lourenço, N. Horta, Best Paper Award at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), "On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies," , in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lisboa, Portugal, June 2016., 01-06-2016
R. M. Martins, N. Lourenço, A. Canelas, R. P. Póvoa, N. Horta, 1st Ranked on “Design Automation Competition” at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), "AIDA: Robust Layout-Aware Synthesis of Analog ICs including Sizing and Layout Generation" at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Istanbul, Turkey., 01-09-2015
R. M. Martins, N. Lourenço, N. Horta, Silver Leaf Best Paper Award at IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME), “Analog IC Placement using Absolute Coordinates and a Hierarchical Combination of Pareto Optimal Fronts”, in IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME), Glasgow, Scotland, June 2015., 01-07-2015
R. P. Póvoa, N. Lourenço, N. Horta, JG Goes, Nominee for Best Student Paper Award at IEEE International Symp. on Circuits and Systems (ISCAS), A Voltage-Combiners-Biased Amplifier with Enhanced Gain and Speed using Current Starving, Lisboa, Portugal., 01-05-2015
R. P. Póvoa, R. Lourenço Lourenço, N. Lourenço, A. Canelas, R. M. Martins, N. Horta, Best Student Paper Award Runner-Up at IEEE International Symp. on Circuits and Systems (ISCAS), LC-VCO Automatic Synthesis Using Multi-Objective Evolutionary Techniques, Melbourne, Australia., 01-06-2014
R. M. Martins, N. Lourenço, S. R. Rodrigues, J.G. Guilherme, N. Horta, Honourable Mention on “Design Automation Competition” at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), “AIDA: Automated Analog IC Design Flow from Circuit Level to Layout”, in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Seville, Spain, Sep. 2012., 01-09-2012
DG Guilherme, J.G. Guilherme, N. Horta, Best Student Paper Award, The International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design - SM2ACD 2010 - best student paper award for the paper entitled ''Automatic Topology Selection and Sizing of Class-D Loop-Filters for Minimizing Distortion'', 01-10-2010

3Miscellaneous

N. Horta, "Behavioral Pattern Detection Using Compact and Fast Methods" by Nuno Homem, PhD Thesis Jury, 01-10-2011
N. Horta, ''Time-Domain Optimizationof Amplifiers based on Distributed Geneti Algorothms'' by Rui Tavares, PhD Thesis Jury, 01-12-2010
N. Horta, "Order Reduction of Parameterized Structured EM-based Linear Models" by Jorge Vilhena, PhD Thesis Jury, 01-09-2010

3Tutorials

N. Horta, N. Lourenço, Analog IC Design Automation: Approaches and Challenges
N. Horta, Evolutionary Computation applied to Analog IC Design Automation
N. Horta, Evolutionary Computation applied to Analog IC Design Automation

Other Contributions

29Conference Committees

IEEE PhD. Research in Microelectronics and Electronics - PRIME, Scientific Committee, 2018
International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Technical Programme Chairman, 2018
Design, Automation, and Test in Europe - DATE, Technical Programme Committee, 2018
IEEE PhD. Research in Microelectronics and Electronics - PRIME, Organizing Committee, 2017
International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Technical Programme Chairman, 2017
Design, Automation, and Test in Europe - DATE, Technical Programme Committee, 2017
IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Conference Chairman, 2016
IEEE PhD. Research in Microelectronics and Electronics - PRIME, Conference Chairman, 2016
Design, Automation, and Test in Europe - DATE, Technical Programme Committee, 2016
Design, Automation, and Test in Europe - DATE, Technical Programme Committee, 2015
IEEE International Symp. on Circuits and Systems - ISCAS, Organizing Committee, 2015
International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Scientific Committee, 2012
International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design - SM2ACD, Scientific Committee, 2010
Design, Automation and Test in Europe Conf., Scientific Committee, 2008
International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design - SM2ACD, Scientific Committee, 2008
Design Automation and Test in Europe, DATE 2007, Technical Programme Committee, 2007
XATA2007 — XML: Aplicações e Tecnologias Associadas, Scientific Committee, 2007
Design Automation and Test in Europe, DATE 2006, Technical Programme Committee, 2006
XATA2006 — XML: Aplicações e Tecnologias Associadas, Scientific Committee, 2006
International Workshop on Symbolic Methods and Applications to Circuit Design - SMACD, Scientific Committee, 2006
5th Conference on Telecommunications, Technical Programme Committee, 2005
Design Automation and Test in Europe, DATE 2005, Technical Programme Committee, 2005
8th International Workshop on Symbolic Methods and Applications to Circuit Design, SMACD 2004, Scientific Committee, 2004
Design Automation and Test in Europe, DATE 2004, Scientific Committee, 2004
Design Automation and Test in Europe, DATE 2003, Scientific Committee, 2003
7th International Workshop on Symbolic Methods and Applications to Circuit Design, SMACD 2002, Scientific Committee, 2002
Design Automation and Test in Europe, DATE 2002, Scientific Committee, 2002
Workshop on System Design Automation, SDA 2000, Technical Programme Committee, 2000
6th International Workshop on Symbolic Methods and Applications to Circuit Design, SMACD 2000, Conference Chairman, 2000

IT Member Profile

Nuno Horta

Bio

Scientific Achievements

As Supervisor

As Co-supervisor

As Supervisor

As Co-supervisor

As Supervisor

As Co-supervisor

Currently running projects2

Closed Projects13