Nuno Cavaco Gomes Horta

Nuno Horta

Academic position:	Associate Professor
Joining date:	01-01-1999
Roles in IT:	Senior Researcher
Scientific Area:	Basic Sciences and Enabling Technologies
Group:	Integrated Circuits - Lx

Email: Send Email
Address: IT – Lisboa
Instituto Superior Técnico - Torre Norte - Piso 10
Av. Rovisco Pais, 1
1049 - 001 Lisboa
Tel: +351 21 841 84 54
Fax: +351 21 841 84 72

https://www.orcid.org/0000-0002-1687-1447

RESEARCHER ID SCOPUS SCHOLAR

Bio

Nuno Horta (S’89–M’97–SM’11) received the Licenciado, MSc, PhD and Habilitation degrees in electrical engineering from Instituto Superior Técnico (IST), University of Lisbon, Portugal, in 1989, 1992, 1997 and 2014, respectively. He is an Associate Professor at IST Electrical and Computer Engineering Department. He is a Senior Researcher at Instituto de Telecomunicações, where he is the head of the Integrated Circuits Group. He has supervised more than 90 post graduation works between MSc and PhD theses. He has authored or co-authored more than 150 publications as books, book chapters, international journals papers and conferences papers. He has also participated as researcher or coordinator in several National and European R&D projects. He was General Chair of AACD 2014, PRIME 2016 and SMACD 2016 and was member of the organizing and technical program committees of several other conferences, e.g., IEEE ISCAS, IEEE LASCAS, DATE, NGCAS, etc. He is Associated Editor of Integration, The VLSI Journal, from Elsevier, and usually acts as reviewer of several prestigious publications, e.g., IEEE TCAD, IEEE TEC, IEEE TCAS, ESWA, ASC, etc. His research interests are mainly in analog and mixed-signal IC design, analog IC design automation, soft computing and data science.

Scientific Achievements

Degrees

Agregação, Instituto Superior Técnico, 09-09-2014
PhD, Instituto Superior Técnico, 24-07-1997
MSc, Instituto Superior Técnico, 30-11-1992
Licenciatura, Instituto Superior Técnico, 31-07-1989

Expertise Topics

Electronic Design Automation
Computer Architectures
Computational Intelligence
Computational Finance

Affiliations

ACM - Association for Computing Machinery, 01-11-2004, Senior Member
Instituto Superior Técnico, 01-03-1998, Associate Professor with Habilitation
Instituto de Telecomunicações, 01-09-1997, Senior Researcher
IEEE - Institute of Electrical and Electronics Engineers, 01-01-1991, Senior Member

Academic Activities

10Lecture courses

Arquitectura de Computadores, , Mestrado em Engenharia Electrotécnica e de Computadores
Sistemas Digitais, , Mestrado em Engenharia Electrotécnica e de Computadores
ANALOG AND MIXED-SIGNAL IC DESIGN AUTOMATION , , PhD Elect e Computadores
Arquitecuras Avançadas de Computadores, , Mestrado em Engenharia Electrotécnica e de Computadores
Multi-Objective Optimization Using Evolutionary, Instituto Superior Técnico, PhD Program in Electrical and Computer Engineering
Analog IC Design Automation, Instituto Superior Técnico, PhD Program in Electrical and Computer Engineering
Computer Architecture, , Integrated Master Degree (MSc) in Electrical and Computer Engineering
Computer Architecture, Instituto Superior Técnico, Integrated Master Degree (MSc) in Electrical and Computer Engineering
Digital Systems, Instituto Superior Técnico, Integrated Master Degree (MSc) in Electrical and Computer Engineering
Advanced Computer Architectures, Instituto Superior Técnico, Integrated Master Degree (MSc) in Electrical and Computer Engineering

Supervision of theses

6PhD Student

Analog IC Design Automation in Deep Nanometer Technologies, PhD Student, António Canelas, 04-2019

Arquitecturas Reconfiguráveis de Elevado Desempenho p/ Terminais Móveis da 4G e 5G, PhD Student, Mauro Edgar Pereira Figueiredo Santos, 05-2018

A New Family of CMOS Cascode-Free Amplifiers with High Energy-Efficiency and Gain Improvement, PhD Student, Ricardo Filipe Sereno Póvoa, 04-2018

AIDA-L: Automatic Analog Integrated Circuits Layout Generator, PhD Student, Ricardo Miguel Ferreira Martins, 07-2015

Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects, PhD Student, Nuno Calado Correia Lourenço, 12-2014

Síntese e Optimização Automática de Circuitos e Sistemas Baseada em Técnicas de Computação Evolutiva, PhD Student, Manuel Fernando Martins de Barros, 05-2009

34MSc Student

Using generic cell libraries to improve the automatic sizing of operational amplifier with rail-to-rail input and output, MSc Student, Nuno Miguel Rodrigues Machado, 11-2017
Exploring Cloud Computing Benefits when Applying a SAX/GA Approach to Computational Finance Problems, MSc Student, Bernardo Gomes, 10-2017
E-CONF: Sistema de Gestão de Conferências, MSc Student, João Pedro Martins Morais Luís, 11-2016
Design of Bandgap Voltage Reference with Curvature Compensation for the Space Industry, MSc Student, Jonathan Felipe Perez Calvillo, 11-2016
Automatic sizing of continuous-time comparators using a generic cell library, MSc Student, José Manuel Moutinho Cachaço, 11-2016
SPACE-DC/DC - II: Conversor DC-DC para a Industria Aeroespacial , MSc Student, Andre Martins Ribeiro, 07-2016
AIDA-C: Evolutionary Optimization Techniques applied to Analog IC Design, MSc Student, André Ferreira, 06-2016
Design of a radiation hardened curvature compensated bandgap adjustable through OTP, MSc Student, António Fitas, 06-2016
Design of behavioral models, transistor level schematic and simulation benches for innovative analog design flow based on IT / AIDA-C, MSc Student, Telmo Oliveira, 06-2016
AIDA-C: Cluster Computing applied to Circuit Level Synthesis and Simulation, MSc Student, David Neves, 10-2015
AIDA-X: Aplicação de Software para Extracção de Netlists de Layouts de Circuitos Interados Analógicos, MSc Student, Bruno Cardoso, 05-2015
DC-DC Converter for the Aerospace Industry, MSc Student, Bruno Silva, 05-2014
Technology Commercialization in the Area of Analog IC Design Automation, MSc Student, Miguel Costa, 05-2014
AIDA-CMK: Multi-Algorithm Optimization Kernel applied to Analog IC Sizing, MSc Student, Ricardo Lourenço, 05-2014
Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel, MSc Student, Frederico Rocha, 12-2012
AIDA II: OpAmps Automatic Layout Generator , MSc Student, Ricardo Martins, 04-2012
Space DCDC - III, MSc Student, Gonçalo Aguiar, 11-2011
AUDIO II: Amplificador Hi-Fi para Audio Portátil de Elevada Eficiência , MSc Student, João Silva Carvalho, 11-2011
EVOLUTION - IC Design Automation, MSc Student, Carla Sofia Paiva Duarte, 04-2011
Space DCDC - II, MSc Student, Bruno Miguel Tavares Silva, 03-2011
Amplificador Hi-Fi para Audio Portátil de Elevada Eficiência, MSc Student, Frederico Bernardes da Silva Tavares Cadete, 03-2011
STOCKS: Computação Inteligente aplicada à Gestão de Portefólios de Acções, MSc Student, Adriano Simões, 12-2010
PLASTIC: Projecto de Circuitos Integrados Orgânicos, MSc Student, António Matos Tavares Proença, 04-2010
MFUNDS: Computação Inteligente aplicada à Gestão de Fundos de Investimento, MSc Student, António Gorgulho, 11-2009
Modelação Inteligente de Circuitos e Sistemas Integrados Analógicos com Recurso a Sistemas Difusos, MSc Student, Pedro Sousa, 10-2009
Conversores DC-DC para a Industria Aeroespacial - II, MSc Student, António Bañon, 05-2009
Conversores DC-DC para a Industria Aeroespacial - I, MSc Student, Carlos Pires, 10-2008
COIN: Computação Inteligente aplicada à Gestão de Fundos de Investimento, MSc Student, Nuno Lopes, 10-2008

LAYGEN: Gerador de Layout com Recurso a Técnicas de Computação Evolutiva, MSc Student, Nuno Calado Correia Lourenço, 11-2007

Conversores A/D Reconfiguráveis para a 4G de Sistemas de Telecomunicações, MSc Student, Artur Silva, 10-2007
AIDA - Automação do Fluxo de Projecto de Circuitos Integrados Analógicos, MSc Student, Gonçalo Neves, 06-2006
Sistema para Gestão Inteligente de Informação numa Plataforma de E-Learning com Recurso a Técnicas de Data Mining, MSc Student, Rui Luís, 01-2006
Sistema para Gestão Inteligente de Conteúdos numa Plataforma de E-Learning, MSc Student, David Simões, 07-2005
Semantic Service Discovery on Smart Home Environments, MSc Student, José Iria, 02-2004

4BSc Student

EVOLUTION: Optimização Automática de Circuitos e Sistemas Integrados, BSc Student, Filipe Alves, 12-2006
Análise e Síntese Simbólica de Circuitos e Sistemas Electrónicos: Métodos Matriciais , BSc Student, Nelson Silva, 11-2004
Sistema para Gestão Inteligente de Conteúdos numa Plataforma de E-Learning, BSc Student, David Simões, 07-2003
Semantic Service Discovery on Smart Home Environments, BSc Student, José Iria, 07-2002

Co-Supervision of theses

1PhD Student

Optimal Stock Market Investments Based on Evolutionary Computation Techniques and Technical Analysis, PhD Student, José Manuel Matias Pinto, 11-2016

25MSc Student

Combining Many-Objective Evolutionary Algorithms in a distributed environment using Many Objectives, Many Processors, MSc Student, Francisco Miguel Gonçalves António de Campos Leal, 12-2019
EDA to the cloud –a case study to increase both effectiveness and user experience of EDA tools., MSc Student, Pedro Baptista Sacadura Biscaia, 05-2018
Enhanced Analog and RF IC Sizing Methodology using PCA and NSGA-II Optimization Kernel, MSc Student, Tiago Claro Oliveira Miranda Pessoa, 11-2017
Using Naive Bayes and Genetic Algorithms to Find Influential Twitter Uses to Forecast the S&P 500, MSc Student, Daniel Jorge Martins Sousa, 06-2017
Using Sentiment from Twitter optimized by Genetic Algorithms to Predict the Stock Market , MSc Student, Carlos Vieira Simões, 05-2017
Detection of Fraud and Corruption in Healthcare System, MSc Student, João Amorim Queirós Galamba de Oliveira, 05-2017
Using a Genetic Algorithm with Options Data to Forecast Stocks, MSc Student, André Filipe Ferreira Duarte, 11-2016
Classification and Clustering of Stocks, using Genetic Algorithms and Fundamental Analysis, MSc Student, David Bugalho de Moura, 11-2016
Detection of Fraud, Abuse and Cost Inefficiencies in the National Healthcare System, MSc Student, Francisco Guerreiro Gomes Pedreira, 11-2016
Parallel Genetic Algorithms for Financial Pattern Discovery using GPUs, MSc Student, João Manuel Fitas Baúto, 11-2016
Combining Support Vector Machine with Genetic Algorithms to Optimize Investments in Forex Markets with High Leverage, MSc Student, Bernardo Martins Paiva Jubert de Almeida, 10-2016
Investimento em OPVs utilizando Análise de Sentimento do Twitter otimizado por Algoritmos Genéticos, MSc Student, Bruno Miguel Filipe Guilherme, 10-2016
An Evolutionary Computing Approach to Financial Portfolio Management Based on Growth Stocks & Sector/Industry Distribution, MSc Student, André Nicolau Fernandes, 05-2016
Growth Stock Portfolio Optimization Using a Multi-Objective EA, MSc Student, Jeffrey Christian Alexander Goedhuys, 05-2016
Combining Rules between PIPs and SAX to Identify Patterns in Financial Markets, MSc Student, João Maria Rodrigues Leitão, 05-2016
Forecasting Stock Returns Based on Event Detection from Twitter, MSc Student, Mariana Gonçalves Alves Daniel, 05-2016
Estratégia de Investimento Value Optimizada por Algoritmos Genéticos Distribuídos, MSc Student, Helder de Oliveira Mota, 11-2015
Developing Multi-Time Frame Trading Rules with a Trend Following Strategy, using GP, MSc Student, Jaime Machado, 11-2015
Análise de padrões em Mercados Bolsistas optimizado por algoritmos genéticos utilizando SAX modificado, MSc Student, Tiago Miguel Marques Branco, 11-2015
CRESCIMENTO- Estratégia de investimento baseada em ações de forte crescimento, MSc Student, Fabio Rubem Sendim, 05-2015
Forex Market Prediction Using Multi Discrete Hidden Markov Models , MSc Student, José Pedro de Oliveira Alves, 05-2015
Combined Pattern Recognition and Genetic Algorithms for Day Trading Strategy, MSc Student, e Daniel Gonzalez Albarran, 05-2013
FOLLOW - Aplicação de Modelos para Seguir Misseis aos Mercados Bolsistas , MSc Student, Pedro Miguel Assis Pereira dos Santos, 11-2010
ADC de Alta Resolução Sigma delta, MSc Student, Antonio Ribeiro, 10-2008
Conversor Concorrencial Analogico Digital de Baixa Potência de Muito Alta Velocidade , MSc Student, Ricardo Gama, 09-2008

2Research Grant

Organic Integrated Circuits, Research Grant, Samuel Pinto, 07-2006
Organic Integrated Circuits-II, Research Grant, Vitor Pelado, 07-2006

Publications

12Books

J. Baúto, R. Neves, N. Horta, Parallel Genetic Algorithms for Financial Pattern Discovery Using GPUs, Springer, lisboa, 2018,
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J. Leitao, R. Neves, N. Horta, Identifying Patterns in Financial Markets: New Approach Combining Rules Between PIPs and SAX, Springer, Lisboa, 2018,
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R. Póvoa, JG Goes, N. Horta, A New Family of Cascode-Free Amplifiers with High Energy-Efficiency and Gain Improvement, Springer, Cham, Switzerland, 2018,
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N. Lourenço, R. M. Martins, N. Horta, Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects, Springer International Publishing, Switzerland, 2017,
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R. M. Martins, N. Lourenço, N. Horta, Analog Integrated Circuit Design Automation – Placement, Routing and Parasitic Extraction Techniques, Springer International Publishing, Switzerland, 2017,
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A. Silva Silva, R. Neves, N. Horta, Portfolio Optimization Using Fundamental Indicators Based on Multi-Objective EA, Springer, Heidelberg, 2016,
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R. Lourenço Lourenço, N. Lourenço, N. Horta, AIDA-CMK: Multi-Algorithm Optimization Kernel applied to Analog IC Sizing, Springer, Heidelberg, New York, London, 2015,
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F. Rocha, R. M. Martins, N. Lourenço, N. Horta, Electronic Design Automation of Analog ICs combining Gradient Models with Multi-Objective Evolutionary Algorithms, Springer, Heidelberg, 2014,
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A. Gorgulho Gorgulho, R. Neves, N. Horta, Intelligent Financial Portfolio Composition based on Evolutionary Computation Strategies, Springer, Heidelberg, 2013,
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A. Canelas, R. Neves, N. Horta, Investment Strategies Optimization based on a SAX-GA Methodology, Springer, Heidelberg, 2013,
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R. M. Martins, N. Lourenço, N. Horta, Generating Analog IC Layouts with LAYGEN II, Springer, n/a, 2013,
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M.B. Barros, J.G. Guilherme, N. Horta, Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques, Springer, Berlin, 2010,
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10Books Chapters

J. Pinto, R. Neves, N. Horta, MULTI-OBJECTIVE OPTIMIZATION OF TRADING STRATEGIES USING GENETIC ALGORITHMS IN UNSTABLE ENVIRONMENTS, Chapter in, New Developments in Evolutionary Computation Research, Nova Publisher, Hauppauge, New York., 2015
J.G. Guilherme, N. Horta, Automatic Layout Optimizations for Integrated MOSFET Power Stages, Chapter in, Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, Springer, Switzerland, 2015
C. Silva, J.G. Guilherme, N. Horta, Nonlinearities Behavioral Modeling and Analysis of Pipelined ADC Building Blocks, Chapter in, Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design, Springer, Switzerland, 2015
N. Leite Leite, R. Neves, N. Horta, F. Melício Melício, A.C.R. Rosa, Solving a Capacitated Exam Timetabling Problem Instance using a Bi-objective NSGA-II, Chapter in, Studies in Computational Intelligence, Kurosh Madani, António Dourado, Agostinho Rosa, Joaquim Filipe, Springer, Heidelberg, 2014
A. Canelas, R. M. Martins, R. Póvoa, N. Lourenço, J.G. Guilherme, N. Horta, Enhancing an Automatic Analog IC Design Flow by using a Technology-Independent Module Generator, Chapter in, Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Maria Helena Fino, IGI global, Medical Information Science Reference, 2014
R. Póvoa, N. Lourenço, A. Canelas, R. M. Martins, N. Horta, Synthesis of LC-Oscillators using Rival Multi-Objective/Multi-Constraint Optimization Kernels, Chapter in, Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Maria Helena Fino, IGI global, Medical Information Science Reference, 2014
N. Lourenço, R. M. Martins, M.B. Barros, N. Horta, Analog Circuit Design based on Robust POFs using an Enhanced MOEA with SVM Models, Chapter in, Analog/RF and Mixed-Signal Circuit Systematic Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Rafael Castro-Lopez, Springer, Heidelberg, 2013
P. Parracho Parracho, A. Canelas, R. Neves, N. Horta, Optimized Uptrend and Downtrend Pattern Templates for Financial Markets Trading Based on a GA Kernel, Chapter in, Financial Markets: Recent Developments, Emerging Practices and Future Prospects, Mohsen Bahmani-Oskooee and Sahar Bahmani, Nova Publisher, 2013
M. Mauro, N. Horta, AMS Synthesis Using Symbolic Methods, Chapter in, Design of Analog Circuits through Symbolic Analysis, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Francisco V. Fernández, Bentham Science Publishers, 2012
N. Horta, C.A. Leme, J.E. Franca, Automated High Level Synthesis of Data Conversion Systems, Chapter in, ANALOGUE-DIGITAL ASICs circuit techniques, design tools and applications, IEE - Peter Peregrinus, IEE Press, 1991

38Papers in Journals

R. M. Martins, N. Lourenço, N. Horta, J. Y. Yin, P. M. Mak, R. P. M. Martins, Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow- Phase-Noise Cellular Applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 1, pp. 69 - 82, January, 2019,
| Abstract | BibTex
J. Carapuço, R. Neves, N. Horta, Reinforcement learning applied to Forex trading, Applied Soft Computing, Vol. 73, No. 1, pp. 783 - 794, December, 2018 | BibTex
A. Canelas, R. Póvoa, R. M. Martins, N. Lourenço, J.G. Guilherme, J.P.C Carvalho, N. Horta, FUZYE: A Fuzzy C-Means Analog IC Yield Optimization using Evolutionary-based Algorithms, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. n/a, No. n/a, pp. 1 - 13, November, 2018,
| Abstract | BibTex
J. Baúto, R. Neves, N. Horta, Parallel SAX/GA for financial pattern matching using NVIDIA’s GPU, Expert Systems with Applications, Vol. 105, No. 1, pp. 77 - 88, September, 2018 | BibTex
F. P. Passos, R. M. Martins, N. Lourenço, E. Roca, R. Póvoa, A. Canelas, R. C.-L. Castro-López, N. Horta, F. V. F, Fernández, Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology, Integration, The VLSI Journal, Vol. 63, No. n/a, pp. 351 - 361, September, 2018,
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J.G. Guilherme, J. Calvillo, R. Póvoa, N. Horta, Second-order compensation BGR with low TC and high performance for space applications, Integration, The VLSI Journal, Vol. 1, No. 1, pp. 1 - 10, July, 2018,
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R. M. Martins, N. Lourenço, F. P. Passos, R. Póvoa, A. Canelas, E. Roca, R. Castro-López, J. S. Sieiro, F. Fernández, N. Horta, Two-Step RF IC Block Synthesis with Pre-Optimized Inductors and Full Layout Generation In-the-loop, IEEE Transactions on Computer-Aided Design, Vol. Early Access, No. Early Access, pp. Early Access - Early Access, May, 2018,
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B. Almeida, R. Neves, N. Horta, Combining Support Vector Machine with Genetic Algorithms to optimize investments in Forex markets with high leverage, Applied Soft Computing, Vol. 64, No. 1, pp. 596 - 613, March, 2018 | BibTex
R. Póvoa, N. Lourenço, R. M. Martins, A. Canelas, N. Horta, JG Goes, Single Stage OTA biased by Voltage-Combiners with Enhanced Performance using Current Starving, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 1, No. 1, pp. 1 - 5, November, 2017 | BibTex
R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Stochastic-based placement template generator for analog IC layout-aware synthesis, Integration, The VLSI Journal, Vol. 58, No. n/a, pp. 485 - 495, June, 2017,
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M. Daniel, R. Neves, N. Horta, Company Event Popularity for Financial Markets Using Twitter and Sentiment Analysis, Expert Systems with Applications, Vol. 71, No. 0, pp. 111 - 124, April, 2017 | BibTex
R. Póvoa, N. Lourenço, R. M. Martins, A. Canelas, N. Horta, J. Goes, Single-Stage Amplifier biased by Voltage-Combiners with Gain and Energy-Efficiency Enhancement, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. PP, No. 99, pp. 1 - 1, March, 2017 | BibTex
J. Leitão, R. Neves, N. Horta, Combining Rules between PIPs and SAX to Identify Patterns in Financial Markets, Expert Systems with Applications, Vol. 65, No. 0, pp. 242 - 254, December, 2016 | BibTex
N. Lourenço, R. M. Martins, A. Canelas, R. Póvoa, N. Horta, AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation, Integration, The VLSI Journal, Vol. 55, No. 09, pp. 316 - 329, September, 2016,
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M. Pandey, A. Canelas, R. Póvoa, J. Torres, J. Costa Freire, N. Lourenço, N. Horta, Design and application of a CMOS active inductor at Ku band based on a multi-objective optimizer, Integration, The VLSI Journal, Vol., No., pp. -, September, 2016 | BibTex
D. Yazdani, A. Moghaddam, A. Dehban, N. Horta, A Novel Approach for Optimization in Dynamic Environments Based on Modified Artificial Fish Swarm Algorithm, International Journal of Computational Intelligence and Applications, Vol. 15, No. 2, pp. 1 - 16, June, 2016,
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R. M. Martins, R. Póvoa, N. Lourenço, N. Horta, Current-flow & Current-Density-aware Multi-Objective Optimization of Analog IC Placement, Integration, The VLSI Journal, Vol. --, No. --, pp. -- - --, June, 2016,
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N Neves, N. Horta, R. Neves, P Tomás, N Roma, Multi-Objective Kernel Mapping and Scheduling for Morphable Many-Core Architectures, Expert Systems with Applications, Vol. 45, No. 1, pp. 385 - 399, March, 2016,
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M. Mauro, N. Horta, J.G. Guilherme, Logarithmic AD Converter with Selectable Transfer Characteristic, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 63, No. 3, pp. 234 - 238, March, 2016,
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R. M. Martins, N. Lourenço, N. Horta, Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates, Expert Systems with Applications, Vol. 42, No. 23, pp. 9137 - 9151, December, 2015,
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J. Pinto, R. Neves, N. Horta, Boosting Trading Strategies Performance using VIX Indicator Together with a Dual-Objective Evolutionary Computation Optimizer, Expert Systems with Applications, Vol. 42, No. 19, pp. 6699 - 6716, November, 2015,
| Abstract | Full text (PDF 2 MBs) | BibTex
M. Fotouhi Ghazvini, J. Soares, N. Horta, R. Neves, R. Castro, Z. Vale, A multi-objective model for scheduling of short-term incentive-based demand response programs offered by electricity retailers, Applied Energy, Vol. 151, No. 1, pp. 102 - 118, August, 2015,
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R. Póvoa, I. Bastos Bastos, N. Lourenço, N. Horta, Automatic Synthesis of RF Front-End Blocks Using Multi-Objective Evolutionary Techniques, Integration, The VLSI Journal, Vol. in press, No. in press, pp. in press - in press, July, 2015,
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N. Magaia, N. Horta, R. Neves, P. Pereira, M. Correia, A multi-objective routing algorithm for Wireless Multimedia Sensor Networks, Applied Soft Computing, Vol. 30, No. 1, pp. 104 - 112, May, 2015,
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A. Silva Silva, R. Neves, N. Horta, A Hybrid Approach to Portfolio Composition based on Fundamental and Technical Indicators”, Expert Systems with Applications, Vol. 42, No. 4, pp. 2036 - 2048, March, 2015,
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N. Lourenço, A. Canelas, R. Póvoa, R. M. Martins, N. Horta, Floorplan-aware analog IC sizing and optimization based on topological constraints, Integration, The VLSI Journal, Vol. 48, No. 1, pp. 183 - 197, January, 2015,
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R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Electromigration-aware analog Router with multilayer multiport terminal structures, Integration, The VLSI Journal, Vol. 47, No. 4, pp. 532 - 547, September, 2014,
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M. Mauro, N. Horta, J.G. Guilherme, A survey on nonlinear analog-to-digital converters, Integration, The VLSI Journal, Vol. 47, No. 1, pp. 12 - 22, January, 2014,
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R. M. Martins, N. Lourenço, N. Horta, LAYGEN II—Automatic Layout Generation of Analog Integrated Circuits, IEEE Transactions on Computer-Aided Design, Vol. 32, No. 11, pp. 1641 - 1654, November, 2013,
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R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Routing analog ICs using a multi-objective multi-constraint evolutionary approach, Analog Integrated Circuits and Signal Processing, Vol. 78, No. 1, pp. 123 - 135, June, 2013,
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A. Canelas, R. Neves, N. Horta, A SAX-GA Approach to Evolve Investment Strategies on Financial Markets based on Pattern Discovery Techniques, Expert Systems with Applications, Vol., No., pp. -, January, 2013,
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DG Guilherme, J.G. Guilherme, N. Horta, Automatic Topology Selection and Sizing of Class-D Loop-Filters for Minimizing Distortion Based on an Evolutionary Optimization Kernel, Analog Integrated Circuits and Signal Processing, Vol. 73, No. 10.1007/s10470-011-9716-4, pp. 21 - 32, October, 2012,
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A. Gorgulho Gorgulho, R. Neves, N. Horta, Applying a GA kernel on optimizing technical analysis rules for stock picking and portfolio composition, Expert Systems with Applications, Vol. 38, No. 11, pp. 14072 - 14085, October, 2011,
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R. Gama, J. Goes, R. Neves, N. Horta, Low-Power Open Loop Multiply-by-two Amplifier with Gain-accuracy Improved by Local-Feedback, Intrnl. Journal of Microelectronics and Computer Science, Vol. 1, No. 1, pp. 19 - 24, June, 2010 | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, Analog Circuits Optimization based on Evolutionary Computation Techniques, Integration, The VLSI Journal, Vol. 43, No. 1, pp. 136 - 155, January, 2010,
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A. Silva, J.G. Guilherme, N. Horta, Reconfigurable multi-mode sigma–delta modulator for 4G mobile terminals, Integration, The VLSI Journal, Vol. 42, No. 1, pp. 34 - 46, January, 2009,
| Abstract | Full text (PDF 1 MB) | BibTex
N. Horta, Analogue and Mixed-Signal Systems Topologies Exploration using Symbolic Methods, Analog Integrated Circuits and Signal Processing, Vol. 31, No. 2, pp. -, February, 2002 | BibTex
N. Horta, J.E. Franca, Algorithm-Driven Synthesis of Data Conversion Architectures, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 16, No. 10, pp. 1116 - 1135, October, 1997 | BibTex

114Papers in Conferences

J.G. Guilherme, J. Z. Zangpo, R. Póvoa, N. Horta, An Integrated LC Oscillator with Self Compensation for Frequency Drift and PVT Corners Variations, IEEE International Conf. on Electronics, Circuits and Integrated Systems - ICECS, Bordeaux, France, Vol. 1, pp. 333 - 336, December, 2018,
| Abstract | Full text (PDF 1 MB) | BibTex
N. Lourenço, J. Rosa, R. M. Martins, H. Aidos, A. Canelas, R. Póvoa, N. Horta, On the Exploration of Promising Analog IC Designs via Artificial Neural Networks, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, Vol., pp. 133 - 136, July, 2018,
| Abstract | BibTex
J.G. Guilherme, R. Granja, M. Mauro, N. Horta, 11.7b Time-To-Digital Converter with 0.82ps resolution in 130nm CMOS Technology, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Prague, Czech Republic, Vol., pp. -, July, 2018,
| Abstract | BibTex
J.G. Guilherme, A. Canelas, R. Póvoa, N. Lourenço, N. Horta, A 20 dB Gain Two-Stage Low-Noise Amplifier with High Yield for 5 GHz Applications, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, Vol., pp. -, July, 2018,
| Abstract | BibTex
F. P. Passos, E. Roca, R. Castro-López, F. Fernández, R. Póvoa, R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, Vol., pp. -, July, 2018 | BibTex
T. Pessoa, N. Lourenço, R. M. Martins, R. Póvoa, N. Horta, Enhanced Analog and RF IC Sizing Methodology using PCA and NSGA-II Optimization Kernel, Design, Automation, and Test in Europe - DATE, Dresden, Germany, Vol., pp. 1 - 4, March, 2018,
| Abstract | Full text (PDF 1 MB) | BibTex
J. Calvillo, J.G. Guilherme, N. Horta, Design of a BGR suitable for The Space Industry with Performance of 1.25 V with 0.758 ppm/°C TC from - 55° to 125°C, New Generation of Circuits and Systems NGCAS, Genova, Italy, Vol., pp. -, September, 2017,
| Abstract | Full text (PDF 1 MB) | BibTex
C. V. S. Simões, R. Neves, N. Horta, Using Sentiment from Twitter optimized by Genetic Algorithms to Predict the Stock Market, IEEE Congress on Evolutionary Computation - CEC, San Sabastian, Spain, Vol. 1, pp. 1 - 8, June, 2017 | BibTex
R. M. Martins, N. Lourenço, R. Póvoa, A. Canelas, N. Horta, F. P. Passos, R. Castro-López, E. Roca, F. Fernández, Layout-Aware Challenges and a Solution for the Automatic Synthesis of Radio-Frequency IC Blocks, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Taormina, Italy, Vol., pp. -, June, 2017,
| Abstract | BibTex
R. Póvoa, A. Canelas, R. M. Martins, N. Lourenço, N. Horta, JG Goes, Dynamic Voltage-Combiners Biased OTA for Low-Power High-Speed SC Circuits, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Taormina, Italy, Vol., pp. -, June, 2017 | BibTex
N. Lourenço, R. M. Martins, R. Póvoa, A. Canelas, N. Horta, F. P. Passos, R. Castro-López, E. Roca, F. Fernández, New Mapping Strategies for Pre-Optimized Inductor Sets in Bottom-Up RF IC Sizing Optimization, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Taormina, Italy, Vol., pp. -, June, 2017,
| Abstract | BibTex
F. P. Passos, R. C.-L. Castro-López, E. Roca, F. V. F, Fernández, R. M. Martins, N. Lourenço, R. Póvoa, A. Canelas, N. Horta, Systematic Design of a Voltage Controlled Oscillator using a Layout-Aware Approach, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Taormina, Italy, Vol., pp. -, June, 2017,
| Abstract | BibTex
A. Canelas, R. M. Martins, R. Póvoa, N. Lourenço, N. Horta, Efficient Yield Optimization Method using a Variable K-Means Algorithm for Analog IC Sizing, Design, Automation, and Test in Europe - DATE, Lausanne, Switzerland, Vol. N/A, pp. 1 - 6, March, 2017,
| Abstract | BibTex
J. Cachaço, N. Machado, N. Lourenço, J.G. Guilherme, N. Horta, Automatic Technology Migration of Analog IC Designs using Generic Cell Libraries, Design, Automation, and Test in Europe - DATE, Lausanne, Switzerland, Vol. N/A, pp. 1 - 4, March, 2017,
| Abstract | BibTex
A. Ferreira, N. Lourenço, R. M. Martins, N. Horta, Automated analog IC design constraints generation for a layout-aware sizing approach, IEEE 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) SMACD, Lisboa, Portugal, Vol. --, pp. 1 - 4, June, 2016,
| Abstract | BibTex
A. Fitas, J.G. Guilherme, N. Horta, Design of a radiation-hardened curvature compensated bandgap reference circuit, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Lisboa, Portugal, Vol. 1, pp. 1 - 4, June, 2016,
| Abstract | BibTex
C. Silva, J.G. Guilherme, N. Horta, SCALES: A high speed simulator tool for pipeline A/D converters, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lisbon, Portugal, Vol. 1, pp. 1 - 4, June, 2016,
| Abstract | BibTex
A. Canelas, R. M. Martins, R. Póvoa, N. Lourenço, N. Horta, Yield Optimization using K-Means Clustering Algorithm to reduce Monte Carlo Simulations, IEEE 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) SMACD, Lisbon, Portugal, Vol. n/a, pp. 1 - 4, June, 2016,
| Abstract | BibTex
R. M. Martins, A. Canelas, N. Lourenço, N. Horta, On-the-fly Exploration of Placement Templates for Analog IC Layout-aware Sizing Methodologies, IEEE 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) SMACD, Lisboa, Portugal, Vol. n/a, pp. 1 - 4, June, 2016 | BibTex
M. Mauro, N. Horta, J.G. Guilherme, An 8bit Logarithmic AD Converter Using Cross- Coupled Inverters and a Time-to-Digital Converter, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Lisbon, Portugal, Vol., pp. 1 - 4, June, 2016,
| Abstract | BibTex
D. Neves, R. M. Martins, N. Lourenço, N. Horta, Design Automation Tasks Scheduling for Enhanced Parallel Execution of a State-of-the-Art Layout-Aware Sizing Approach, Design, Automation, and Test in Europe - DATE, Dresden, Germany, Vol. n/a, pp. 1 - 4, March, 2016,
| Abstract | BibTex
R. M. Martins, N. Lourenço, N. Horta, M. Santos, Embedding Fault List Compression Techniques in a Design Automation Framework for Analog and Mixed-Signal Structural Testing, Conference on Design of Circuits and Integrated Systems DCIS, Estoril, Portugal, Vol. n/a, pp. n/a - n/a, November, 2015,
| Abstract | BibTex
R. M. Martins, R. Póvoa, N. Lourenço, N. Horta, Exploring Design Tradeoffs in Analog IC Placement with Current-Flow & Current-Density Considerations, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. n/a, pp. n/a - n/a, September, 2015,
| Abstract | BibTex
R. M. Martins, N. Lourenço, A. Canelas, R. Póvoa, N. Horta, AIDA: Robust Layout-Aware Synthesis of Analog ICs including Sizing and Layout Generation, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. n/a, pp. n/a - n/a, September, 2015,
| Abstract | BibTex
D. Neves, N. Lourenço, N. Horta, Scheduling evaluation tasks for increased efficiency of parallel analog IC synthesis, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. na, pp. 1 - 4, September, 2015,
| Abstract | BibTex
M. Pandey, A. Canelas, R. Póvoa, J. Torres, J. Costa Freire, N. Lourenço, N. Horta, Grounded Active Inductors Design Optimization for FQmax = 14.2 GHz using a 130 nm CMOS Technology, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. -, pp. 1 - 4, September, 2015 | BibTex
J.M. Machado, R. Neves, N. Horta, Developing Multi-Time Frame Trading Rules with a Trend Following Strategy, using GA, Genetic and Evolutionary Computation Conf. - GECCO, madrid, Spain, Vol. 1, pp. 765 - 766, July, 2015,
| Abstract | BibTex
R. M. Martins, N. Lourenço, N. Horta, Analog IC Placement using Absolute Coordinates and a Hierarchical Combination of Pareto Optimal Fronts, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Glasgow, United Kingdom, Vol., pp. -, June, 2015,
| Abstract | BibTex
B. Cardoso, R. M. Martins, N. Lourenço, N. Horta, AIDA-PEx: Accurate Parasitic Extraction for Layout-Aware Analog Integrated Circuit Sizing, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Glasgow, United Kingdom, Vol., pp. -, June, 2015,
| Abstract | BibTex
R. Póvoa, N. Lourenço, N. Horta, J. Goes, A Voltage-Combiners-Biased Amplifier with Enhanced Gain and Speed using Current Starving, IEEE International Symp. on Circuits and Systems - ISCAS, Lisboa, Portugal, Vol., pp. -, May, 2015 | Full text (PDF 418 KBs) | BibTex
R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Extraction and Application of Wiring Symmetry Rules to Route Analog Multiport Terminals, IEEE International Symp. on Circuits and Systems - ISCAS, Lisboa, Portugal, Vol. n/a, pp. 1945 - 1948, May, 2015,
| Abstract | BibTex
J.G. Guilherme, N. Horta, Thermal-aware floorplanning and layout generation of MOSFET power stages, IEEE International Symp. on Circuits and Systems - ISCAS, Lisbon, Portugal, Vol. 1, pp. 1 - 4, May, 2015,
| Abstract | BibTex
N. Lourenço, R. M. Martins, N. Horta, Layout-Aware Sizing of Analog ICs using Floorplan & Routing Estimates for Parasitic Extraction, Design, Automation and Test in Europe Conf., Grenoble, France, Vol. 0, pp. 1 - 6, March, 2015,
| Abstract | BibTex
R. Póvoa, N. Lourenço, N. Horta, RST Santos Tavares, J. Goes, A Cascode-Free Single-Stage Amplifier using a Fully-Differential Folded Voltage-Combiner, IEEE International Conf. on Electronics, Circuits and Systems, Marselha, France, Vol., pp. -, December, 2014 | BibTex
B. Silva, J.G. Guilherme, N. Horta, A Rad-Hard DC-DC Converter Controller, IEEE International Conf. on Electronics, Circuits and Integrated Systems - ICECS, Marseille, France, Vol. 1, pp. 439 - 442, December, 2014,
| Abstract | BibTex
J.G. Guilherme, N. Horta, Automatic Layout Generation of Power MOSFET Transistors in Bulk CMOS, IEEE International Conf. on Electronics, Circuits and Integrated Systems - ICECS, marseille, France, Vol. 1, pp. 606 - 609, December, 2014,
| Abstract | BibTex
M. Mauro, N. Horta, J.G. Guilherme, Logarithmic AD Conversion Using Latched Comparators and a Time-to-Digital Converter, IEEE International Conf. on Electronics, Circuits and Integrated Systems - ICECS, Marseille, France, Vol., pp. 319 - 322, December, 2014,
| Abstract | BibTex
R. Póvoa, R. Lourenço Lourenço, N. Lourenço, A. Canelas, R. M. Martins, N. Horta, LC-VCO Automatic Synthesis Using Multi-Objective Evolutionary Techniques, IEEE International Symp. on Circuits and Systems - ISCAS, Melbourne, Australia, Vol., pp. -, June, 2014 | BibTex
J. Pinto, R. Neves, N. Horta, Multi-Objective Optimization of Investment Strategies Based on Evolutionary Computation Techniques, in Volatile Environments, International Conf. on Enterprise Information Systems, ICEIS, Lisboa, Portugal, Vol. NA, pp. 480 - 488, April, 2014,
| Abstract | Full text (PDF 707 KBs) | BibTex
A. V. Silva Silva, R. Neves, N. Horta, Portfolio Optimization Using Fundamental Indicators Based on Multi-Objective EA, IEEE Computational Intelligence for Financial Engineering and Economics - CIFEr, London, United Kingdom, Vol. I, pp. 1 - 4, March, 2014 | BibTex
R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures, Design, Automation, and Test in Europe - DATE, Dresden, Germany, Vol. n/a, pp. 1 - 6, March, 2014,
| Abstract | BibTex
R. Póvoa, N. Lourenço, N. Horta, RST Santos Tavares, J. Gomes, Single-Stage Amplifiers with Gain Enhancement and Improved Energy-Efficiency employing Voltage-Combiners, IFIP/IEEE International Conf. on Very Large Scale Integration, Istambul, Turkey, Vol., pp. -, October, 2013,
| Abstract | BibTex
A. Canelas, R. Neves, N. Horta, Multi-Dimensional Pattern Discovery in Financial Time Series using SAX-GA with extended robustness, Genetic and Evolutionary Computation Conf. - GECCO, Amsterdam, Netherlands, Vol. 0, pp. 1 - 3, July, 2013,
| Abstract | BibTex
R. Neves, N. Horta, Optimizing Investment Strategies based on Companies Earnings using Genetic Algorithms, Genetic and Evolutionary Computation Conf. - GECCO, Amsterdam, Netherlands, Vol. 0, pp. 1 - 3, July, 2013,
| Abstract | BibTex
F.C. Cadete, N. Lourenço, M.B. Barros, R. M. Martins, N. Horta, A New Metaheuristc Combining Gradient Models with NSGA-II to Enhance Analog IC Synthesis, IEEE Congress on Evolutionary Computation - CEC, Cancun, Mexico, Vol., pp. -, June, 2013,
| Abstract | BibTex
R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Multi-Port Multi-Terminal Analog Router based on an Evolutionary Optimization Kernel, IEEE Congress on Evolutionary Computation - CEC, Cancún, Mexico, Vol. n/a, pp. 2789 - 2796, June, 2013,
| Abstract | BibTex
F. Rocha, R. Póvoa, N. Lourenço, R. M. Martins, N. Horta, A New Metaheuristc Combining Gradient Models with NSGA-II to Enhance Analog IC Synthesis, IEEE Congress on Evolutionary Computation - CEC, Cancún, Mexico, Vol., pp. -, June, 2013 | BibTex
F.C. Cadete, R. M. Martins, N. Lourenço, N. Horta, Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel, Doctoral Conf. on Computing, Electrical and Industrial Systems - DOCEIS, Lisbon, Portugal, Vol., pp. -, April, 2013,
| Abstract | BibTex
N. Leite Leite, R. Neves, N. Horta, F. Melício Melício, A.C.R. Rosa, Solving an Uncapacitated Exam Timetabling Problem Instance using a Hybrid NSGA-II, International Conf. on Evolutionary Computation Theory and Applications - ECTA, Barcelona, Spain, Vol., pp. -, October, 2012 | BibTex
J.G. Guilherme, C. Silva, N. Horta, SCALES – A Behavioral Simulator for Pipelined Analog-to-Digital Converter Design, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Seville, Spain, Vol. 1, pp. 149 - 152, September, 2012,
| Abstract | BibTex
R. M. Martins, N. Lourenço, N. Horta, Multi-Objective Multi-Constraint Routing of Analog ICs using a Modified NSGA-II Approach, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Seville, Spain, Vol. n/a, pp. 65 - 68, September, 2012,
| Abstract | BibTex
R. M. Martins, N. Lourenço, J.G. Guilherme, N. Horta, AIDA: Automated Analog IC Design Flow from Circuit Level to Layout, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Seville, Spain, Vol. n/a, pp. 29 - 32, September, 2012,
| Abstract | BibTex
O. Y. Yefimochkin, R. Neves, N. Horta, An Evolutionary Approach to Define Investment Strategies based on Macroeconomic Indicators and VIX Data, Genetic and Evolutionary Computation Conf. - GECCO, Philadelphia, United States, Vol., pp. -, July, 2012,
| Abstract | BibTex
A. Canelas, R. Neves, N. Horta, A New SAX-GA Methodology applied to Investment Strategies Optimization, Genetic and Evolutionary Computation Conf. - GECCO, Philadelphia, United States, Vol., pp. -, July, 2012,
| Abstract | BibTex
J. Pinto, N. Horta, Automated Passive Filter Design Using Multi-objective Genetic Algorithms with Variable Parameters, Genetic and Evolutionary Computation Conf. - GECCO, Philadelphia, United States, Vol. NA, pp. NA - NA, July, 2012,
| Abstract | Full text (PDF 356 KBs) | BibTex
N. Lourenço, N. Horta, GENOM-POF: Multi-Objective Evolutionary Synthesis of Analog ICs with Corners Validation, Genetic and Evolutionary Computation Conf. - GECCO, Philadelphia, United States, Vol., pp. 1119 - 1126, July, 2012,
| Abstract | BibTex
R. M. Martins, N. Lourenço, N. Horta, LAYGEN II – Automatic Analog ICs Layout Generator based on a Template Approach, Genetic and Evolutionary Computation Conf. - GECCO, Philadelphia, United States, Vol. n/a, pp. 1127 - 1134, July, 2012,
| Abstract | BibTex
F.C. Cadete, DG Guilherme, J.G. Guilherme, N. Horta, F.C. Cadete, Overcurrent Detection Circuit for Integrated Class-D Amplifiers, European Conf. on Circuit Theory and Design, Linköping, Sweden, Vol. 1, pp. 410 - 413, September, 2011,
| Abstract | BibTex
P. Sousa, C. Duarte, M.B. Barros, J.G. Guilherme, N. Horta, Optimal OpAmp Sizing based on a Fuzzy-Genetic Kernel, Genetic and Evolutionary Computation Conf. - GECCO, Dublin, Ireland, Vol., pp. -, July, 2011,
| Abstract | Full text (PDF 331 KBs) | BibTex
J. Pinto, R. Neves, N. Horta, Fitness Function Evaluation for MA Trading Strategies based on Genetic Algorithms, Genetic and Evolutionary Computation Conf. - GECCO, Dublin, Ireland, Vol. NA, pp. 819 - 820, July, 2011,
| Abstract | Full text (PDF 419 KBs) | BibTex
P. Parracho Parracho, R. Neves, N. Horta, Trading with Optimized Uptrend and Downtrend Pattern Templates using a Genetic Algorithm Kernel, IEEE Congress on Evolutionary Computation - CEC, New Orleans, United States, Vol., pp. -, June, 2011,
| Abstract | Full text (PDF 541 KBs) | BibTex
A. Simões, R. Neves, N. Horta, An Innovative GA Optimized Investment Strategy based on a New Technical Indicator using Multiple MAs, IJCCI International Conf. on Evolutionay Computation - ICEC, Valencia, Spain, Vol. 1, pp. 1 - 4, October, 2010,
| Abstract | Full text (PDF 149 KBs) | BibTex
DG Guilherme, J.G. Guilherme, N. Horta, Automatic Topology Selection and Sizing of Class-D Loop-Filters for Minimizing Distortion, International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design - SM2ACD, Gammarth, Tunisia, Vol. 1, pp. 1 - 4, October, 2010,
| Abstract | BibTex
DG Guilherme, J.G. Guilherme, N. Horta, An Automated Design Methodology for Audio Class-D Loop-Filters Optimized for THD+N, International Analog VLSI Workshop - AVLSIWS, Pavia, Italy, Vol. 1, pp. 47 - 51, September, 2010,
| Abstract | Full text (PDF 404 KBs) | BibTex
P. Parracho Parracho, R. Neves, N. Horta, Trading in Financial Markets using Pattern Recognition Optimized by Genetic Algorithms, Genetic and Evolutionary Computation Conf. - GECCO, Portland, United States, Vol. 1, pp. 1 - 1, July, 2010 | Full text (PDF 268 KBs) | BibTex
P. Sousa, C. Duarte, J.G. Guilherme, N. Horta, Enhancing Analog IC Design Optimization Kernels with Simple Fuzzy Models, European Conf. on Circuit Theory and Design, Antalya, Turkey, Vol., pp. -, August, 2009,
| Abstract | Full text (PDF 340 KBs) | BibTex
P. Sousa, C. Duarte, N. Horta, FUGA: A Fuzzy-Genetic Analog Circuit Optimization, Genetic and Evolutionary Computation Conf. - GECCO, Montreal, Canada, Vol., pp. -, July, 2009,
| Abstract | Full text (PDF 194 KBs) | BibTex
A. Gorgulho Gorgulho, R. Neves, N. Horta, Using GAs to Balance Technical Indicators on Stock, Genetic and Evolutionary Computation Conf. - GECCO, Montreal, Canada, Vol., pp. -, July, 2009,
| Abstract | BibTex
R. Gama, R. Neves, N. Horta, Design of a low-power, open loop, multiply-by-two amplifier with gain-accuracy improved by local-feedback, International Conf. Mixed Design of Integrated Circuits and Systems - MIXDES, Lodz, Poland, Vol. 1, pp. 1 - 5, June, 2009 | Full text (PDF 162 KBs) | BibTex
A. Ribeiro, T. Costa, R. Gama, R. Neves, N. Horta, A bandgap Voltage Reference with Only CMOS Transistors, Conf. on Telecommunications - ConfTele, Santa maria da Feira, Portugal, Vol. I, pp. 69 - 72, May, 2009 | Full text (PDF 125 KBs) | BibTex
T. Costa, R. Neves, N. Horta, Low-Area 4th-Order Shared-Amplfier Sigms-delta Modulator, Conf. on Telecommunications - ConfTele, Santa maria da Feira, Portugal, Vol. I, pp. 65 - 68, May, 2009 | Full text (PDF 192 KBs) | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, Analog Circuits Optimization based on Evolutionary Computation Techniques, Conf. on Telecommunications - ConfTele, Feira, Portugal, Vol. 1, pp. 1 - 1, April, 2009,
| Abstract | BibTex
M. Mauro, C. Pires, J.G. Guilherme, N. Horta, Overview of Radiation Effects and Design Constraints off Fully Custom SMPS, IEEE Asia Pacific Conf. on Circuits and Systems - APCCAS, Macau, China, Vol. 1, pp. 372 - 375, December, 2008,
| Abstract | BibTex
P. Sousa, C. Duarte, N. Horta, Enhancing a GA Optimization Kernel based on Fuzzy Design Rules, International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design - SM2ACD, Erfurt, Germany, Vol., pp. -, October, 2008,
| Abstract | Full text (PDF 524 KBs) | BibTex
N. Horta, M.B. Barros, J.G. Guilherme, Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques, International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design - SM2ACD, Erfurt, Germany, Vol., pp. -, October, 2008,
| Abstract | Full text (PDF 776 KBs) | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, Analog Circuits and Systems Optimization based on Evolutionary Computation Techniques, International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design - SM2ACD, Erfurt, Germany, Vol., pp. 68 - 73, October, 2008,
| Abstract | BibTex
M. Figueira, J.G. Guilherme, N. Horta, Radiation Hardened SMPS, International Workshop on Analog and Mixed-Signal Integrated Circuits for Space Applications - AMICSA, Sintra, Portugal, Vol., pp. -, September, 2008 | BibTex
M. Mauro, C. Pires, J.G. Guilherme, N. Horta, Radiation Hardened SMPS, Power Converter and Integrated Circuit Design Controller, International Workshop on Analog and Mixed-Signal Integrated Circuits for Space Applications - AMICSA, Cascais, Portugal, Vol. 1, pp. 1 - 8, August, 2008,
| Abstract | BibTex
N. Horta, A. Silva, J.G. Guilherme, A Reconfigurable A/D Converter for 4G Wireless, IEEE International Symp. on Circuits and Systems - ISCAS, Seattle, United States, Vol., pp. 924 - 927, May, 2008,
| Abstract | BibTex
N. Horta, A. Silva, J.G. Guilherme, Design of a Multimode Reconfigurable Sigma-Delta Converter for 4G Wireless Receivers, European Conf. on Circuit Theory and Design, , Spain, Vol., pp. -, August, 2007 | BibTex
N. Horta, M.B. Barros, J.G. Guilherme, An Evolutionary Optimization Kernel Using a Dynamic GA-SVM Model Applied to Analog IC Design, European Conf. on Circuit Theory and Design, , Spain, Vol., pp. -, August, 2007 | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, An Evolutionary Optimization Kernel Using a Dynamic GA-SVM Model Applied to Analog IC Design, European Conf. on Circuit Theory and Design, Seville, Spain, Vol., pp. 33 - 35, August, 2007 | BibTex
R. Neves, J.G. Guilherme, N. Horta, Designing Reconfigurable Multi-Standard Analog Baseband Front-End for 4G Mobile Terminals: System Level Design, Conf. on Telecommunications - ConfTele, Peniche, Portugal, Vol. I, pp. 1 - 4, May, 2007 | BibTex
N. Lourenço, N. Horta, LAYGEN - Automatic Analog ICs Layout Generator, Conf. on Telecommunications - ConfTele, Peniche, Portugal, Vol. 0, pp. 165 - 168, May, 2007,
| Abstract | BibTex
N. Horta, A. Charas, J. Morgado, PLASTIC: Automatic Characterization and Modeling of Organic Transistors for IC Design and Simulation, Conf. on Telecommunications - ConfTele, Peniche, Portugal, Vol., pp. -, March, 2007 | BibTex
N. Horta, M.B. Barros, J.G. Guilherme, GA-SVM Feasibility Model and Optimization Kernel applied to Analog IC Design Automation, ACM Great Lakes VLSI - GLSVLSI), , Italy, Vol., pp. -, March, 2007 | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, GA-SVM Feasibility Model and Optimization Kernel applied to Analog IC Design Automation, ACM Great Lakes VLSI - GLSVLSI), Stresa, Italy, Vol., pp. 469 - 472, March, 2007 | BibTex
N. Horta, G. Neves, M.B. Barros, AIDA: Analog IC Design Automation based on a Fully Configurable Design Hierarchy and Flow, IEEE International Conf. on Electronics, Circuits and Systems, , France, Vol., pp. -, December, 2006 | BibTex
N. Horta, M.B. Barros, J.G. Guilherme, GA-SVM Optimization Kernel applied to Analog IC Design Automation, IEEE International Conf. on Electronics, Circuits and Systems, , France, Vol., pp. -, December, 2006 | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, GA-SVM Optimization Kernel applied to Analog IC Design Automation, IEEE International Conf. on Electronics, Circuits and Integrated Systems - ICECS, Nice, France, Vol., pp. 486 - 489, December, 2006 | BibTex
N. Lourenço, M.V. Vianello, J.G. Guilherme, N. Horta, LAYGEN - Automatic Layout Generation of Analog ICs from Hierarchical Template Descriptions, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Otranto, Italy, Vol. 0, pp. 213 - 216, June, 2006,
| Abstract | BibTex
N. Lourenço, N. Horta, LAYGEN – An Evolutionary approach to automatic analog IC Layout Generation, IEEE Conf. on Electronics, Circuits and System, Gammarth, Tunisia, Vol. 1, pp. 1 - 2, December, 2005,
| Abstract | BibTex
N. Horta, G. Neves, Design Automation Methodology for Analog IC Design Matching Designers Approach, International Symp. on Signals, Circuits and Systems, Iasi, Romania, Vol., pp. -, July, 2005 | BibTex
N. Horta, M.B. Barros, An Evolutionary Optimization Kernel with Adaptive Parameters applied to Analog Circuit Design, International Symp. on Signals, Circuits and Systems, Iasi, Romania, Vol., pp. -, July, 2005 | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, An Evolutionary Optimization Kernel with Adaptive Parameters applied to Analog Circuit Design, International Symp. on Signals, Circuits and Systems, Iasi, Romania, Vol. 2, pp. 545 - 548, July, 2005 | BibTex
N. Horta, D. Simões, Evolving Standards in E-Learning: A Case-Study, Conf. on Telecommunications - ConfTele, Tomar, Portugal, Vol., pp. -, April, 2005 | BibTex
N. Horta, M.B. Barros, An Evolutionary Optimization Approach applied to Analog Circuit Design, Conf. on Telecommunications - ConfTele, Tomar, Portugal, Vol., pp. -, April, 2005 | BibTex
N. Horta, Analog and Mixed-Signal IC Design Automation: Synthesis and Optimization Overview, Conf. on Telecommunications - ConfTele, Tomar, Portugal, Vol., pp. -, April, 2005 | BibTex
M.B. Barros, J.G. Guilherme, N. Horta, An Evolutionary Optimization Approach applied to Analog Circuit Design, Conf. on Telecommunications - ConfTele, Tomar, Portugal, Vol., pp. -, April, 2005 | BibTex
N. Horta, M.B. Barros, G. Neves, J.G. Guilherme, A Distributed Enhanced Genetic Algorithm Kernel Applied to a Circuit/Level Optimization EDesign Environment, Conf. on Design of Circuits and Integrated Systems, Bordeaux, France, Vol., pp. -, November, 2004 | BibTex
M.B. Barros, G. Neves, J.G. Guilherme, N. Horta, A Distributed Enhanced Genetic Algorithm Kernel Applied to a Circuit/Level Optimization EDesign Environmen, Conf. on Design of Circuits and Integrated Systems, Bordeaux, France, Vol., pp. 20 - 24, November, 2004 | BibTex
N. Horta, R. Luis, D. Simões, A Multi-Level Model for Tracking Analysis in E-Learning Platforms, IEEE International Conf. on Advanced Learning Technologies, Helsinki, Finland, Vol., pp. -, September, 2004 | BibTex
N. Horta, D. Simões, R. Luis, Enhancing the SCORM Modelling Scope, IEEE International Conf. on Advanced Learning Technologies, Helsinki, Finland, Vol., pp. -, September, 2004 | BibTex
N. Horta, M.B. Barros, J. Silva, G. Neves, Enhanced Genetic Algorithm Kernel Applied to a Circuit-Level Optimization E-Design Environment, IEEE Conf. on Electronics, Circuits and System, Sharjah, United Arab Emirates, Vol., pp. -, December, 2003 | BibTex
N. Horta, J. Redol, R. Luis, D. Simões, Data Warehousing and Data Mining Applied to an E-Learning Platform, International Conf. on Multimedia and ICTs in Education, Badajoz, Spain, Vol., pp. -, December, 2003 | BibTex
M.B. Barros, J. Silva, G. Neves, J.G. Guilherme, N. Horta, Enhanced Genetic Algorithm Kernel Applied to a Circuit-Level Optimization E-Design Environment, IEEE Conf. on Electronics, Circuits and System, Sharjah, United Arab Emirates, Vol., pp. 1046 - 1049, December, 2003 | BibTex
N. Horta, D. Simões, R. Luis, J. Redol, A New Approach Towards E-Learning Contents Standardization And Enhanced Usability, IADIS International Conf. on WWW/Internet, Albufeira, Portugal, Vol. 1, pp. 1199 - 1103, November, 2003 | BibTex
N. Horta, J. Redol, D. Simões, VIANET-A New Web Framework for Distance Learning, IEEE International Conf. on Advanced Learning Technologies, Athens, Greece, Vol., pp. -, July, 2003 | BibTex
R. Neves, N. Horta, Banner - Intelligent Management of Banner Advertisements on the WWW, International Conf. on Data Mining, Florence, Italy, Vol. 1, pp. 11 - 15, September, 2002 | BibTex
N. Horta, J. Iria, Towards a Framework for Semantic Service Discovery in Ubiquitous P2P Environment, International Conf. on Internet Computing, Las Vegas, United States, Vol., pp. -, June, 2002 | BibTex
J. Silva, N. Horta, GENOM: Circuit-Level Optimizer Based on a Modified Genetic Algorithm Kernel, IEEE International Symp. on Circuits and Systems - ISCAS, Phoenix, Arizona, United States, Vol., pp. -, May, 2002 | BibTex
J. Silva, N. Horta, E-Design Front-End for an IC optimizer based on a Genetic Algorithm, European Workshop on Microelectronics Education, Vigo, Spain, Vol., pp. -, May, 2002 | BibTex
M. Fino, N. Horta, Symbolic Techniques Applied to Switched-Current ADCs Synthesis, IEEE International Symp. on Circuits and Systems - ISCAS, Geneve, Switzerland, Vol. 1, pp. 1124 - 1127, May, 2000 | BibTex
J.G. Guilherme, N. Horta, Symbolic Synthesis of Non-Linear Data Converters, IEEE International Conf. on Electronics, Circuits and Systems, Lisbon, Portugal, Vol. 3, pp. 219 - 222, September, 1998 | BibTex

Projects

Currently running projects1

Acronym	Name	Funding Agency	Start date	Ending date
AIDA-C	AIDA-C: Analog IC Optimizer	Thales Alenia Space	01-10-2013	01-11-2021

Closed Projects11

Acronym	Name	Funding Agency	Start date	Ending date
AIDA	AIDA – Automated P-Cell Generation based on Multi-Objective Optimization and Pareto Optimal Front Circuit Level Characterization	IT/LA	01-10-2011	01-12-2013
AISMAD	AISMAD – Advanced Integrated Switched-Mode Audio Drivers	IT/LA	01-07-2011	01-12-2013
DISRUPTIVE	DISRUPTIVE - A Paradigm Shift in the Design of Analog and Mixed-Signal Nanoelectronic Circuits and Systems	FCT	01-04-2013	01-12-2016
EVOLUTION	Exploring Evolutionary Computation to Enhance Analog IC Design Automation Methodologies	FCT/POSC	01-08-2005	31-07-2007
HEAD	HEAD – Integrated Class D Audio Amplifier with High Efficiency	IT/LA	01-11-2008	01-11-2010
LAYGEN	Automatic Layout Generation of Mixed-Signal ICs	IT/LA	01-04-2006	31-03-2008
OPERA	OPERA - Layout-Aware Analog IC Design Automation	IT/LA	01-03-2014	01-02-2016
PLASTIC	Fully Patterned all Plastic Integrated Circuits	IT/LA	01-07-2005	01-09-2007
SCALES	SCALES - Simulation Tool for Pipeline ADCs	Thales Alenia Space	01-04-2011	01-04-2014
Space-DCDC	Space-DCDC – DC-DC controller for space applications	IT/LA	01-10-2008	01-10-2010
SPEED	Low Power Ultra-High Speed Analogue-to-Digital Converter for Ultra-Wideband Wireless Communications	FCT/PTDC	01-09-2007	01-03-2011

Other Scientific Achievements

7Awards

J. Calvillo, J.G. Guilherme, N. Horta, Silver Leaf Award, Silver Leaf Award for Design of a BGR suitable for The Space Industry with Performance of 1.25 V with 0.758 ppm/°C TC from - 55° to 125°C in New Generation of Circuit and Systems Conference., 01-09-2017
R. M. Martins, A. Canelas, N. Lourenço, N. Horta, Best Paper Award at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), "On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies," , in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lisboa, Portugal, June 2016., 01-06-2016
R. M. Martins, N. Lourenço, A. Canelas, R. Póvoa, N. Horta, 1st Ranked on “Design Automation Competition” at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), "AIDA: Robust Layout-Aware Synthesis of Analog ICs including Sizing and Layout Generation" at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Istanbul, Turkey., 01-09-2015
R. M. Martins, N. Lourenço, N. Horta, Silver Leaf Best Paper Award at IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME), “Analog IC Placement using Absolute Coordinates and a Hierarchical Combination of Pareto Optimal Fronts”, in IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME), Glasgow, Scotland, June 2015., 01-07-2015
R. Póvoa, R. Lourenço Lourenço, N. Lourenço, A. Canelas, R. M. Martins, N. Horta, Best Student Paper Award Runner-Up at IEEE International Symp. on Circuits and Systems - ISCAS, LC-VCO Automatic Synthesis Using Multi-Objective Evolutionary Techniques, 01-06-2014
R. M. Martins, N. Lourenço, S. R. Rodrigues, J.G. Guilherme, N. Horta, Honourable Mention on “Design Automation Competition” at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), “AIDA: Automated Analog IC Design Flow from Circuit Level to Layout”, in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Seville, Spain, Sep. 2012., 01-09-2012
DG Guilherme, J.G. Guilherme, N. Horta, Best Student Paper Award, The International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design - SM2ACD 2010 - best student paper award for the paper entitled ''Automatic Topology Selection and Sizing of Class-D Loop-Filters for Minimizing Distortion'', 01-10-2010

3Miscellaneous

N. Horta, "Behavioral Pattern Detection Using Compact and Fast Methods" by Nuno Homem, PhD Thesis Jury, 01-10-2011
N. Horta, ''Time-Domain Optimizationof Amplifiers based on Distributed Geneti Algorothms'' by Rui Tavares, PhD Thesis Jury, 01-12-2010
N. Horta, "Order Reduction of Parameterized Structured EM-based Linear Models" by Jorge Vilhena, PhD Thesis Jury, 01-09-2010

3Tutorials

N. Horta, N. Lourenço, Analog IC Design Automation: Approaches and Challenges
N. Horta, Evolutionary Computation applied to Analog IC Design Automation
N. Horta, Evolutionary Computation applied to Analog IC Design Automation

Other Contributions

29Conference Committees

IEEE PhD. Research in Microelectronics and Electronics - PRIME, Scientific Committee, 2018
International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Technical Programme Chairman, 2018
Design, Automation, and Test in Europe - DATE, Technical Programme Committee, 2018
IEEE PhD. Research in Microelectronics and Electronics - PRIME, Organizing Committee, 2017
International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Technical Programme Chairman, 2017
Design, Automation, and Test in Europe - DATE, Technical Programme Committee, 2017
IEEE 2016 13th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD) SMACD, Conference Chairman, 2016
IEEE PhD. Research in Microelectronics and Electronics - PRIME, Conference Chairman, 2016
Design, Automation, and Test in Europe - DATE, Technical Programme Committee, 2016
Design, Automation, and Test in Europe - DATE, Technical Programme Committee, 2015
IEEE International Symp. on Circuits and Systems - ISCAS, Organizing Committee, 2015
International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Scientific Committee, 2012
International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design - SM2ACD, Scientific Committee, 2010
Design, Automation and Test in Europe Conf., Scientific Committee, 2008
International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design - SM2ACD, Scientific Committee, 2008
Design Automation and Test in Europe, DATE 2007, Technical Programme Committee, 2007
XATA2007 — XML: Aplicações e Tecnologias Associadas, Scientific Committee, 2007
Design Automation and Test in Europe, DATE 2006, Technical Programme Committee, 2006
XATA2006 — XML: Aplicações e Tecnologias Associadas, Scientific Committee, 2006
International Workshop on Symbolic Methods and Applications to Circuit Design - SMACD, Scientific Committee, 2006
5th Conference on Telecommunications, Technical Programme Committee, 2005
Design Automation and Test in Europe, DATE 2005, Technical Programme Committee, 2005
8th International Workshop on Symbolic Methods and Applications to Circuit Design, SMACD 2004, Scientific Committee, 2004
Design Automation and Test in Europe, DATE 2004, Scientific Committee, 2004
Design Automation and Test in Europe, DATE 2003, Scientific Committee, 2003
7th International Workshop on Symbolic Methods and Applications to Circuit Design, SMACD 2002, Scientific Committee, 2002
Design Automation and Test in Europe, DATE 2002, Scientific Committee, 2002
Workshop on System Design Automation, SDA 2000, Technical Programme Committee, 2000
6th International Workshop on Symbolic Methods and Applications to Circuit Design, SMACD 2000, Conference Chairman, 2000

IT Member Profile