Ready-to-Fabricate RF and mmWave Integrated Circuit Layouts LAY(RF)^2

Project: Ready-to-Fabricate RF and mmWave Integrated Circuit Layouts

Acronym: LAY(RF)^2

Main Objective:
The LAY(RF)^2 proposes the research, development and test of highly accurate and efficient methods for the automation of radio frequency (RF) and millimeter wave (mmWave) integrated circuit (IC) building blocks. This will be achieved by bringing together the previous work from the involved research teams, and, the knowledge of its members in the areas of: analog, mixed-signal, RF/mmWave IC design in deep nanometer technologies; electronic design automation (EDA); physics and modeling of semiconductor devices; computational intelligence; and also, machine learning (ML). The starting point for LAY(RF)^2 project is AIDASoft, an EDA tool developed by the ICG-Lx research team on the course of several IT projects. However, the latest developments in RF/mmWave IC domains and technologies are bringing new and complex challenges that must be mandatorily incorporated within EDA tools functionalities. The proposed automatic layout-aware methodology with ready-to-fabricate prototypes in-the-loop will be the most complete EDA solution for RF and mmWave IC design to date. While providing fully-automatic functionalities based on advanced computational intelligent and ML techniques, its target is not to drive designers away from their current workspace, but instead, to exploit the full capabilities of well-known and established off-the-shelf CAD tools, i.e., circuit simulator, electromagnetic simulator, DRC, LVS checker, and, layout extractor. By automatically exploring the ready-to-fabricate post-layout design space, re-design iterations can be successfully eliminated, bringing RF/mmWave circuit blocks closer to a first-pass fabrication success as every structure required for tape-out is considered and balanced during the optimization process, ultimately: (1) decreasing design time; (2) reducing design costs; (3) decreasing errors; and, (4) achieving optimal or near-optimal circuit performances.

Reference: UIDB/EEA/50008/2020

Funding: IT

Start Date: 01-02-2020

End Date: 31-01-2022

Team: Ricardo Miguel Ferreira Martins, Fábio Moreira de Passos, Nuno Cavaco Gomes Horta, Nuno Calado Correia Lourenço, João Manuel Torres Caldinhas Simões Vaz, Marco António da Mota Carvalho Silva Pereira, Luís Miguel Moreira Mendes, Alexandra Sofia Martins de Carvalho, Marta Isabel Belchior Lopes, Pui-In Mak, Jun Yin, Javier Sieiro

Groups: Integrated Circuits - Lx, Wireless Circuits – Lx, Pattern and Image Analysis – Lx

Partners: Grup de Radiofreqüència, Universitat de Barcelona (ES), State-Key Laboratory of Analog and Mixed-Signal VLSI, FST-ECE Macau (CN)

Local Coordinator: Ricardo Miguel Ferreira Martins

United Nations Strategic Development Goal - Industry, Innovation and Infrastructure

Associated Publications

Books2
F. Passos, E. Roca, R. Castro-López, F. V. Fernandez Fernandez, Automated Hierarchical Synthesis of Radio-Frequency Integrated Circuits and Systems, Springer International Publishing, New York, 2020,
| BibTex
A. Gusmão, N. Horta, N. Lourenço, R. M. Martins, Analog IC Placement Generation via Neural Networks from Unlabeled Data, Springer International Publishing, Lisbon, 2020,
| BibTex

11Papers in Journals
R. M. Martins, N. Lourenço, Analog Integrated Circuit Routing Techniques: An Extensive Review, IEEE Access, Vol. 11, No. 0, pp. 35965 - 35983, April, 2023,
| Abstract | BibTex
A. Gusmão, R. Vieira, N. Horta, N. Lourenço, R. M. Martins, Exploiting a Deep Learning Toolbox for Human-Machine Feedback towards Analog Integrated Circuit Placement Automation, Electronics, Vol. 11, No. 23, pp. 1 - 1, November, 2022,
| Abstract | BibTex
A. Gusmão, N. Horta, N. Lourenço, R. M. Martins, Scalable and order invariant analog integrated circuit placement with Attention-based Graph-to-Sequence deep models, Expert Systems with Applications, Vol. 207, No. 1, pp. 117954 - 117954, November, 2022 | Full text (PDF 4 MBs) | BibTex
A. Gusmão, R. P. Póvoa, N. Horta, N. Lourenço, R. M. Martins, DeepPlacer: A custom integrated OpAmp placement tool using deep models, Applied Soft Computing Journal, Vol. 115, No. 1, pp. 108188 - 108188, January, 2022,
| Abstract | BibTex
A. Canelas, F. Passos, N. Lourenço, R. M. Martins, E. Roca, R. Castro-López, N. Horta, F. V. Fernandez Fernandez, Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs, IEEE Access, Vol. 9, No. 1, pp. 124152 - 124164, September, 2021,
| Abstract | BibTex
L. Mendes, J. Vaz, F. Passos, N. Lourenço, R. M. Martins, In-Depth Design Space Exploration of 26.5-to-29.5-GHz 65-nm CMOS Low-Noise Amplifiers for Low-Footprint-and-Power 5G Communications Using One-and- Two -Step Design Optimization, IEEE Access, Vol. 9, No. --, pp. 70353 - 70368, May, 2021,
| Abstract | Full text (PDF 3 MBs) | BibTex
R. M. Martins, N. Lourenço, R. P. Póvoa, N. Horta, Shortening the gap between pre- and post-layout analog IC performance by reducing the LDE-induced variations with multi-objective simulated quantum annealing, Engineering Applications of Artificial Intelligence, Vol. 98, No. n/a, pp. 104102 - 104102, February, 2021,
| Abstract | BibTex
E. Afacan, N. Lourenço, R. M. Martins, G. Dundar, Review: Machine learning techniques in analog/RF integrated circuit design, synthesis, layout, and test, Integration, the VLSI Journal, Vol. -, No. -, pp. - - -, November, 2020,
| Abstract | BibTex
R. M. Martins, N. Lourenço, N. Horta, J. Y. Yin, P. M. Mak, R. P. M. Martins, Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 67, No. 11, pp. 3965 - 3977, November, 2020,
| Abstract | BibTex
F. Passos, E. Roca, R. M. Martins, N. Lourenço, S. Ahyoune Ahyoune, J. S. Sieiro, R. Castro-López, N. Horta, F. V. Fernandez Fernandez, Ready-to-Fabricate RF Circuit Synthesis Using a Layout- and Variability-Aware Optimization-Based Methodology, IEEE Access, Vol. 8, No. -, pp. 51601 - 51609, March, 2020 | BibTex
F. Passos, M. Cahnca, E. Roca, R. Castro-López, F. V. Fernandez Fernandez, Synthesis of mm-Wave Wideband Receivers in 28nm CMOS Technology for Automotive Radar Applications, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. -, No. -, pp. 1 - 1, January, 2020 | BibTex

10Papers in Conferences
F. Passos, R. M. Martins, N. Lourenço, L. Mendes, J. Vaz, N. Horta, Efficient Hierarchical mm-Wave System Synthesis with Embedded Accurate Transformer and Balun Machine Learning Models, Asia and South Pacific Design Automation Conference ASP-DAC, Tokyo, Japan, January, 2023,
| Abstract | BibTex
F. Passos, N. Lourenço, R. M. Martins, E. Roca, R. Castro-López, N. Horta, F. V. Fernandez Fernandez, Machine Learning Approaches for Transformer Modeling, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Villasimius, Italy, June, 2022 | BibTex
Alves P. Alves, A. Gusmão, N. Horta, N. Lourenço, R. M. Martins, ANN-based Analog IC Floorplan Recommender with a Broader Topological Constraints Coverage, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Sardinia, Italy, Vol., pp. -, June, 2022,
| Abstract | Full text (PDF 898 KBs) | BibTex
L. Mendes, J. Vaz, F. Passos, N. Lourenço, R. M. Martins, Automatic Design of High-Gain 26.5-to-29.5-GHz Transformer-Less Low-Noise Amplifier 1.86-to-8.87-mW Variants in 65-nm CMOS, IEEE International Symposium on Circuits and Systems ISCAS, Austin, United States, May, 2022,
| Abstract | BibTex
L. Mendes, J. Vaz, F. Passos, N. Lourenço, R. M. Martins, Automatic Design of High-Gain 26.5-to-29.5-GHz Transformer-Less Low-Noise Amplifier 1.86-to-8.87-mW Variants in 65-nm CMOS, IEEE International Symposium on Circuits and Systems ISCAS, Austin, United States, May, 2022,
| Abstract | BibTex
A. Gusmão, N. Horta, N. Lourenço, R. M. Martins, Late Breaking Results: Attention in Graph2Seq Neural Networks towards Push-Button Analog IC Placement, ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, United States, December, 2021,
| Abstract | BibTex
R. M. Martins, A. Gusmão, A. Canelas, F. Passos, N. Lourenço, N. Horta, An Essay on the Next Generation of Performance-driven Analog/RF IC EDA Tools: The Role of Simulation-based Layout Optimization, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Erfurt, Germany, July, 2021,
| Abstract | BibTex
A. Gusmão, N. Lourenço, R. M. Martins, N. Horta, Bringing Structure into Analog IC Placement with Relational Graph Convolutional Networks, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Conference online, July, 2021,
| Abstract | BibTex
A. Gusmão, A. Canelas, N. Horta, N. Lourenço, R. M. Martins, A Deep Learning Toolbox for Analog Integrated Circuit Placement, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Conference online, July, 2021,
| Abstract | BibTex
A. Gusmão, N. Lourenço, R. M. Martins, N. Horta, F. Passos, R. P. Póvoa, Semi-Supervised Artificial Neural Networks towards Analog IC Placement Recommender, IEEE International Symposium on Circuits and Systems ISCAS, Sevilla, Spain, October, 2020,
| Abstract | BibTex

3Theses
Speeding-Up Complex RF IC Sizing Optimizations with a Process, Voltage and Temperature Corner Performance Estimator using Deep ANNs, Instituto Superior Técnico, MSc Student, Pedro José da Costa Diogo Caldinhas Vaz, Supervisor: R. M. Martins, Co-supervisor: N. Horta, fev-2021 - out-2021
ANN-based Floorplan Recommender for Large Analog IC Building Blocks with Multiple Topological Constraints Coverage, Instituto Superior Técnico, MSc Student, Pedro José Borges Alves, Supervisor: R. M. Martins, Co-supervisor: N. Horta, fev-2021 - out-2021
Accelerating Voltage-Controlled Oscillator Sizing Optimizations with a Convergence Classifier & Frequency Guess Predictor, Instituto Superior Técnico, MSc Student, João Luís Carreira Pich Domingues, Supervisor: R. M. Martins, Co-supervisor: N. Horta, fev-2021 - out-2021

Project / LAY(RF)^2

Project: Ready-to-Fabricate RF and mmWave Integrated Circuit Layouts