FPGA-based Design and Optimization of a 5G-NR DU Receiver
FPGA-based Design and Optimization of a 5G-NR DU Receiver, Proc Telecoms Conference ConfTELE, Leiria, Portugal, Vol. , pp. - , February, 2021.
Digital Object Identifier: https://doi.org/10.1109/ConfTELE50222.2021.9435579
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In this paper, a Fifth-Generation New Radio (5G-NR) Distributed Unit (DU) receiver case study is carried out to evaluate the trade-offs between different design parameters. The 5G-NR DU receiver is modelled using a fast implementation flow, from the behavioral model to the Field-Programmable Gate Array (FPGA) validation. The goal of this paper is to optimize the area, power, and DU receiver overall performance of the Register-Transfer Level (RTL) implementations from a high-level model by varying the model input data type, i.e., the number of quantized bits at the input of the processing chain. Matlab and Simulink are used to implement the 5G-NR DU behavioral model, and its synthesis is performed by the Hardware Description Language (HDL) Coder automated tool. The 5G-NR DU receiver is implemented in a ZCU102 evaluation kit, containing an XCZU9EG-FFVB1156-2-E device. The trade-offs are evaluated by analyzing the Error Vector Magnitude (EVM), the coarse symbol timing detection, the resource utilization, the power, throughput, the maximum operating frequency, and the latency for different modulation schemes. The results showed a direct dependence of the input data type on these design parameters, while the modulation scheme is almost agnostic, providing reliable information for an optimized DU implementation.