Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling
Póvoa , R. P.
Martins, R. M.
Architectural Design for Heartbeat Detection Circuits using Verilog-A Behavioral Modeling, Proc IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD SMACD, Sardinia, Italy, Vol. , pp. - , June, 2022.
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This work presents a study of two analog front-end circuit architectures for heartbeat detection. Both circuits present an amplification block as the first stage, followed by a band-pass filter. In the first, the heartbeat detection is done
using an adaptive threshold based on pulse-width, whereas the heartbeat detection in the second is done using a sample and hold to find the maximum and minimum peak of each beating. Both architectures are modeled in Verilog-A and simulated using real-world ECG signals with different characteristics. This work studies possible fundamental analog circuit blocks suitable for wearable implementation. It evaluates critical performances requirements from the analysis of the behavior simulations. It was verified that the first circuit can properly detect heartbeats as long as the input-referred noise is below 21 μV, whereas the second one ensures it until 30 μV. The low cutoff frequency can be approximately 10 Hz without compromising the signal’s peaks, which means that these specifications can be relaxed substantially compared to systems intended to reconstruct the signal accurately.