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LAYGEN - Automatic Layout Generation of Analog ICs from Hierarchical Template Descriptions

Lourenço, N. ; Vianello, M.V. ; Guilherme, J.G. ; Horta, N.

LAYGEN - Automatic Layout Generation of Analog ICs from Hierarchical Template Descriptions, Proc IEEE PhD. Research in Microelectronics and Electronics - PRIME, Otranto, Italy, Vol. 0, pp. 213 - 216, June, 2006.

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Abstract
This paper describes an innovative analog IC layout generation tool based on evolutionary computation techniques. The proposed approach starts by a high level layout description (template), which is independent from technology, although including expert knowledge as placement and routing constrains. Then, based on the set of constrain rules provided by the designer through the template, the layout is automatically generated using an evolutionary kernel. Additionally, a module generated is also included in order to allow the automatic generation of different instances for each device in the layout template, therefore, automatically enlarging the solution search space. The LAYGEN tool is here presented and demonstrated for the layout generation of typical circuit structures