Abstract1— This paper describes an innovative analog IC layout
generation tool based on evolutionary computation techniques.
The designer provides a high level layout description. This
template contains placement and routing constrains and is
independent from technology. This expert knowledge is used to
guide an evolutionary optimization kernel during the automatic
generation of the layout for the target technology. Additionally,
this template can be used hierarchically in the definition of
templates for more complex circuits. The LAYGEN tool is here
presented and demonstrated for the layout generation of typical
circuit structures.