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Automatic Layout Generation of Power MOSFET Transistors in Bulk CMOS

Guilherme, J.G. ; Horta, N.

Automatic Layout Generation of Power MOSFET Transistors in Bulk CMOS, Proc IEEE International Conf. on Electronics, Circuits and Integrated Systems - ICECS, marseille, France, Vol. 1, pp. 606 - 609, December, 2014.

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Abstract
This paper presents an automatic layout
generation tool for power MOSFET transistors in bulk CMOS. It
is implemented in an open multiplatform language, Python, and
is capable of generating area and power optimized transistors,
which automatically meet DRC, DFM and ESD rule sets. The tool
is able to fast create technology independent layouts, easily
ported between technology nodes, and directly export designs
into GDSII format, allowing complete independence from any IC
design platform. The tool is demonstrated in a design of a halfbridge power stage for a Class-D amplifier and compared with a reference manual design - the results obtained are superior: lower resistance and dynamic power losses, while keeping almost the same overall area but speeding-up the design flow by several orders of magnitude.