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Scheduling evaluation tasks for increased efficiency of parallel analog IC synthesis

Neves, D. ; Lourenço, N. ; Horta, N.

Scheduling evaluation tasks for increased efficiency of parallel analog IC synthesis, Proc International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. na, pp. 1 - 4, September, 2015.

Digital Object Identifier: 10.1109/SMACD.2015.7301700

Abstract
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This paper presents a methodology to increase the efficiency of automatic analog integrated circuit synthesis and optimization including simultaneously sizing; layout; and worst case corners, by using the multiple CPUs that are cheaply available in today's workstations. While most individual tools, for example circuit simulators already provide some sort of multi-processor capability, the efficiency of holistic solutions that incorporate both the sizing, layout, parasitic extraction and worst case performance evaluation can be further extended by proper use of the available computational resources. Moreover, due to licensing costs, the number of instances of each tool is usually limited. By efficiently scheduling the synthesis tasks over the available processing elements, these scarce resources (licenses) are used optimally. The proposed approach was verified with the evaluation flow of AIDA, for the simultaneous layout and worst case corner aware synthesis of a typical analog circuit showing an improvement of about 20% in processing time when compared to the trivial parallelization.