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Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models

Saraza-Canflanca, P. ; Malagon, D. ; Passos, F. ; Toro-Frias, A. ; Nuñez, J. ; Diaz-Fortuny, J. ; Castro-López, R. ; Roca, E. ; Martin-Martinez, J. ; Rodriguez, R. ; Nafria, M. ; Fernandez, F. V. Fernandez

Design Considerations of an SRAM Array for the Statistical Validation of Time-Dependent Variability Models, Proc IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, Vol. , pp. - , July, 2018.

Digital Object Identifier: 10.1109/SMACD.2018.8434900

Abstract
Modeling and characterization of time-dependent variability phenomena as well as the simulation of their impact on circuit operation have attracted considerable efforts. This paper digs into the validation of compact models and simulation tools in the real operation of circuits. One of the most popular blocks, the 6T SRAM, is proposed for this purpose and a test chip containing an SRAM array is designed. The array allows individual access to each SRAM cell, the application of accelerated aging tests as well as the characterization of common performance metrics.