Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications
Martins, R. M.
; Yin, J. Y.
; Mak, P. M.
; Martins, R. P. M.
Design and Optimization of a Class-C/D VCO for Ultra-Low-Power IoT and Cellular Applications, Proc IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, Vol. , pp. - , July, 2018.
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The proper analysis of design tradeoffs of Voltage-controlled oscillators (VCOs) embedded in state-of-the-art multistandard transceivers is tedious and impractical, as a large amount of conflicting performance figures obtained from multiple modes, test benches and/or analysis must be considered simultaneously. In this paper, the performance boundaries of a complex dual-mode class-C/D VCO are extended using a framework for automatic sizing of radio-frequency (RF) integrated circuit (IC) blocks, where an all-inclusive test bench formulation enhanced with a measurement processing system enables the optimization of “everything-at-once” towards its true optimal tradeoffs. The dual-mode design and optimization conducted provided 512 design solutions with figures-of-merit above 192 dBc/Hz, pushing this topology to its performance limits on a 65 nm technology, by reducing 24% of the power consumption of the original design, while also showing its potential for ultra-low power, with more than 94% reduction.