An Essay on the Next Generation of Performance-driven Analog/RF IC EDA Tools: The Role of Simulation-based Layout Optimization
Martins, R. M.
;
Gusmão, A.
;
Canelas, A.
;
Passos, F.
;
Lourenço, N.
;
Horta, N.
An Essay on the Next Generation of Performance-driven Analog/RF IC EDA Tools: The Role of Simulation-based Layout Optimization, Proc IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Erfurt, Germany, Vol. , pp. - , July, 2021.
Digital Object Identifier: 978-3-8007-5588-2
Abstract
Despite the fact that analog and radio-frequency (A/RF) integrated circuit (IC) design automation has been intensively studied in the last few decades, only automatic circuit-level sizing methodologies have achieved a satisfactory level of maturity. Layout and its countless issues have challenged all automation attempts, and two limiting factors must be addressed to force their way into the industrial environment: plug-and-play capabilities and accurate assessment of post-layout performance degradation. This paper brainstorms around the idea of developing the ultimate fully automatic “performance-driven” A/RF IC synthesis by incorporating simulation-based layout optimization concepts in the flow. The essay is carried the PONDEROUS tool, a novel and highly integrated, but exceptionally computationally intensive, placement A/RF IC optimizer.
