This paper presents a new analog polynomial pre-distortion circuit using 350nm CMOS technology to reduce the distortion of the power amplifier in wireless communication systems. The proposed pre-distortion circuit uses the polynomial approach. The coefficients of the polynomial are controlled by multiplying them with sufficient digit defined through the indirect learning process to provide best practice linearization. Circuit level simulation of the proposed circuit is using Cadence DFW II is used as proof of concept. The simulation set-up comprises a power amplifier, excited with a four carrier GSM signal, pre-distorted by the proposed circuit. Simulation results show that using the pre-distortion circuit the 3rd order intermodulation distortion is reduced on average by 12 and 16 dB.