Substrate noise isolation improvement in a single-well standard CMOS process
Santos, P. M.
Integration, the VLSI Journal Vol. 52, Nº -, pp. 122 - 128, January, 2016.
ISSN (print): 0167-9260
Journal Impact Factor: 0,703 (in 2015)
Digital Object Identifier: 10.1016/j.vlsi.2015.09.006
This work describes a fully CMOS compatible methodology, which makes available a pseudo deep n-well in single-well standard CMOS process. The proposed method is based on mask manipulation to accommodate the field implant p-type region into the n-well, and does not require any additional masks or modification in the CMOS process flow. According to the experimental results, the floating NMOS made available by the methodology shows a reduction in the threshold voltage, which implies a slight improvement in its performance, when compared with its standard NMOS counterpart. It was also experimentally demonstrated up to 3 GHz, that the guard-ring field implant/pseudo deep n-well pro- posed structure improves substrate noise isolation when compared to the classical p+ guard-ring, with a maximum improvement above 20 dB for low frequencies and a minimum of 4 dB at 3 GHz.