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Stochastic-based placement template generator for analog IC layout-aware synthesis

Martins, R. M. ; Lourenço, N. ; Canelas, A. ; Horta, N.

Integration, The VLSI Journal Vol. 58, Nº n/a, pp. 485 - 495, June, 2017.

ISSN (print): 0167-9260
ISSN (online): 0167-9260

Journal Impact Factor: 0,703 (in 2015)

Digital Object Identifier: 10.1016/j.vlsi.2017.02.012

Abstract
In this paper, a methodology for automatic generation of placement templates for analog integrated circuit design targeted to state-of-the-art optimization-based layout-aware circuit-sizing flows, is proposed. The multi-objective optimization-based placement template generator inputs a Pareto set of sizing solutions and outputs a set of optimal sizing-independent non-slicing B*-tree floorplan representations, i.e., placement templates. Those templates fit the current state of the optimization process and are used within the layout-aware synthesis methodology to generate the floorplan of the following candidate solutions. This innovative methodology combines the advantages of template-based placement approaches, due to its fast packing, with the optimization-based ones, presenting floorplan solutions with improved compactability through the complete evolution of the Pareto set, completely eliminating the template setup effort. Moreover, as the placement template generator runs in parallel with the layout-aware loop, it has no impact on the overall execution time. Experimental results show that the proposed methodology outperforms state-of-the-art multi-template layout-aware synthesis approaches by achieving smaller placement areas for the same performances earlier in the optimization, and further, with a strongly reduced setup effort.