Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs
Martins, R. M.
; Roca, E.
; Castro-López, R.
; Fernandez, F. V. Fernandez
IEEE Access Vol. 9, Nº 1, pp. 124152 - 124164, September, 2021.
ISSN (print): 2169-3536
Scimago Journal Ranking: 0,93 (in 2021)
Digital Object Identifier: 10.1109/ACCESS.2021.3110758
This paper presents an innovative yield-aware synthesis strategy based on a hierarchical bottom-up methodology that uses a multiobjective evolutionary optimization algorithm to design a complete radiofrequency integrated circuit from the passive component level up to the system level. Within it, performances’ calculation aims for the highest possible accuracy. A surrogate model calculates the performances for the inductive devices, with accuracy comparable to full electromagnetic simulation; and, an electrical simulator calculates circuit- and system-level performances. Yield is calculated using Monte-Carlo (MC) analysis with the foundry-provided models without any model approximation. The computation of the circuit yield throughout the hierarchy is estimated employing parallelism and reducing the number of simulations by performing MC analysis only to a reduced number of candidate solutions, alleviating the computational requirements during the optimization. The yield of the elements not accurately evaluated is assigned using their degree of similitude to the simulated solutions. The result is a novel synthesis methodology that reduces the total optimization time compared to a complete MC yield-aware optimization. Ultimately, the methodology proposed in this work is compared against other methodologies that do not consider yield throughout the system’s complete hierarchy, demonstrating that it is necessary to consider it over the entire hierarchy to achieve robust optimal designs.