Creating and sharing knowledge for telecommunications

DeepPlacer: A custom integrated OpAmp placement tool using deep models

Gusmão, A. ; Póvoa , R. P. ; Horta, N. ; Lourenço, N. ; Martins, R. M.

Applied Soft Computing Journal Vol. 115, Nº 1, pp. 108188 - 108188, January, 2022.

ISSN (print): 1568-4946
ISSN (online):

Scimago Journal Ranking: 1,88 (in 2022)

Digital Object Identifier: 10.1016/j.asoc.2021.108188

Mechanisms towards the automatic analog integrated circuit layout design have been an intensive research topic in the past few decades. Still, the industrial environment has no automatic approach established. The advances of machine learning applications in electronic design automation come with the promise to change this reality. This paper proposes a deep learning generative model for the placement “optimization” of analog integrated circuit basic blocks. The model behaves as an argmin operator for the placement cost function and can provide placement solutions instantly. Moreover, the model can be fed with unlabeled data, greatly facilitating data collection. A generic and innovative circuits’ representation at the network’s input layer is proposed, encoding the devices’ dimensions, connectivity, and topological constraints. Besides, the randomness found in generative models is embedded directly into the feature vector, as the order of the features per device is shuffled in the input vector. Shuffling the order of the devices’ features in the input not only brings multi-modality but also solves a generalization problem, as there is not any natural order defined to place devices in the feature vector. As a proof of concept, a deep artificial neural network capable of proposing different placement solutions, in less than 150 ms each, for six amplifier topologies and, in multiple technology nodes ranging from 350 nm down to 65 nm, is demonstrated. DeepPlacer was capable of producing correct solutions for topologies and technology nodes not present in the training set, showing good generalization while not hindering circuit performance due to the placement.