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Floorplan-aware analog IC sizing and optimization based on topological constraints

Lourenço, N. ; Canelas, A. ; Póvoa , R. P. ; Martins, R. M. ; Horta, N.

Integration, the VLSI Journal Vol. 48, Nº 1, pp. 183 - 197, January, 2015.

ISSN (print): 0167-9260
ISSN (online): 0167-9260

Journal Impact Factor: 0,703 (in 2015)

Digital Object Identifier: 10.1016/j.vlsi.2014.07.002

Abstract
This paper presents a methodology for analog IC circuit-level sizing and optimization, which takes into account the layout geometrical properties, by introducing a simple and general description that permits the inclusion of the floorplan generation in the sizing optimization loop with negligible computational costs. The usage of a modified NSGA-II state-of-the-art multi-objective multi-constraint optimization kernel enables the efficient exploration of design tradeoffs, while the inclusion of corner cases and the usage of the industrial circuit simulators (HSPICE®, Eldo® or Spectre®) ensures the accuracy and reliability of the solutions. Several layout templates that enclose the constraints defined by the designer are used to generate multiple floorplan solutions for each sizing solution during the synthesis process, giving the optimizer pertinent and accurate geometric layout information, e.g., area, width, length, wasted area, etc. Additionally, a built-in technology independent module generator facilitates the instantiation of multiple versions of each device, further increasing the exploration of possible geometric combinations and consequently packing of the floorplan with a minimum of wasted area. The developed tool, AIDA-C, implements the proposed approach, and is validated for both classical and new analog circuit structures using the UMC 130 nm design process.