Ricardo Miguel Ferreira Martins

Ricardo Martins

Academic position:	Post. Doc.
Joining date:	01-09-2011
Roles in IT:	Researcher
Scientific Area:	Basic Sciences and Enabling Technologies
Group:	Integrated Circuits - Lx

Email: Send Email
Address: IT – Lisboa
Instituto Superior Técnico - Torre Norte - Piso 10
Av. Rovisco Pais, 1
1049 - 001 Lisboa
Tel: +351 21 841 84 54
Fax: +351 21 841 84 72

https://www.orcid.org/0000-0002-8251-1415

SCOPUS SCHOLAR LinkedIn

Scientific Achievements

Degrees

PhD, Instituto Superior Técnico, 21-07-2015

Expertise Topics

Analog Integrated Circuits Design Automation

Academic Activities

Supervision of theses

1MSc Student

Deep Learning and Analog Layout Synthesis , MSc Student, Daniel José Domingos Guerra, Concluded 10-2018

Co-Supervision of theses

5MSc Student

Combining Many-Objective Evolutionary Algorithms in a distributed environment using Many Objectives, Many Processors, MSc Student, Francisco Miguel Gonçalves António de Campos Leal, Expected conclusion 12-2019
Applied Bayesian optimization, MSc Student, Filipe Cláudio de Sousa, Concluded 05-2018
Deep learning in analog IC automatic sizing, MSc Student, João Pedro da Silva Rosa, Concluded 05-2018
EDA to the cloud –a case study to increase both effectiveness and user experience of EDA tools., MSc Student, Pedro Baptista Sacadura Biscaia, Concluded 05-2018
Enhanced Analog and RF IC Sizing Methodology using PCA and NSGA-II Optimization Kernel, MSc Student, Tiago Claro Oliveira Miranda Pessoa, Concluded 11-2017

Publications

4Books

N. Lourenço, R. M. Martins, N. Horta, Automatic Analog IC Sizing and Optimization Constrained with PVT Corners and Layout Effects, Springer International Publishing, Switzerland, 2017,
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R. M. Martins, N. Lourenço, N. Horta, Analog Integrated Circuit Design Automation – Placement, Routing and Parasitic Extraction Techniques, Springer International Publishing, Switzerland, 2017,
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F. Rocha, R. M. Martins, N. Lourenço, N. Horta, Electronic Design Automation of Analog ICs combining Gradient Models with Multi-Objective Evolutionary Algorithms, Springer, Heidelberg, 2014,
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R. M. Martins, N. Lourenço, N. Horta, Generating Analog IC Layouts with LAYGEN II, Springer, n/a, 2013,
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3Books Chapters

A. Canelas, R. M. Martins, R. P. Póvoa, N. Lourenço, J.G. Guilherme, N. Horta, Enhancing an Automatic Analog IC Design Flow by using a Technology-Independent Module Generator, Chapter in, Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Maria Helena Fino, IGI global, Medical Information Science Reference, 2014
R. P. Póvoa, N. Lourenço, A. Canelas, R. M. Martins, N. Horta, Synthesis of LC-Oscillators using Rival Multi-Objective/Multi-Constraint Optimization Kernels, Chapter in, Performance Optimization Techniques in Analog, Mixed-Signal, and Radio-Frequency Circuit Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Maria Helena Fino, IGI global, Medical Information Science Reference, 2014
N. Lourenço, R. M. Martins, M.B. Barros, N. Horta, Analog Circuit Design based on Robust POFs using an Enhanced MOEA with SVM Models, Chapter in, Analog/RF and Mixed-Signal Circuit Systematic Design, Mourad Fakhfakh, Esteban Tlelo-Cuautle, Rafael Castro-Lopez, Springer, Heidelberg, 2013

15Papers in Journals

R. P. Póvoa, N. Lourenço, R. M. Martins, A. Canelas, N. Horta, JG Goes, A Folded Voltage-Combiners Biased Amplifier for Low Voltage and High Energy-Efficiency Applications, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 1, No. 1, pp. 1 - 5, April, 2019,
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R. M. Martins, N. Lourenço, N. Horta, J. Y. Yin, P. M. Mak, R. P. M. Martins, Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow- Phase-Noise Cellular Applications, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 1, pp. 69 - 82, January, 2019,
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A. Canelas, R. P. Póvoa, R. M. Martins, N. Lourenço, J.G. Guilherme, J.P.C Carvalho, N. Horta, FUZYE: A Fuzzy C-Means Analog IC Yield Optimization using Evolutionary-based Algorithms, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. n/a, No. n/a, pp. 1 - 13, November, 2018,
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F. P. Passos, R. M. Martins, N. Lourenço, E. Roca, R. P. Póvoa, A. Canelas, R. C.-L. Castro-López, N. Horta, F. V. F, Fernández, Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology, Integration, the VLSI Journal, Vol. 63, No. n/a, pp. 351 - 361, September, 2018,
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R. M. Martins, N. Lourenço, F. P. Passos, R. P. Póvoa, A. Canelas, E. Roca, R. Castro-López, J. S. Sieiro, F. Fernández, N. Horta, Two-Step RF IC Block Synthesis with Pre-Optimized Inductors and Full Layout Generation In-the-loop, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. Early Access, No. Early Access, pp. Early Access - Early Access, May, 2018,
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R. P. Póvoa, N. Lourenço, R. M. Martins, A. Canelas, N. Horta, JG Goes, Single Stage OTA biased by Voltage-Combiners with Enhanced Performance using Current Starving, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 1, No. 1, pp. 1 - 5, November, 2017,
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R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Stochastic-based placement template generator for analog IC layout-aware synthesis, Integration, the VLSI Journal, Vol. 58, No. n/a, pp. 485 - 495, June, 2017,
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R. P. Póvoa, N. Lourenço, R. M. Martins, A. Canelas, N. Horta, J. Goes, Single-Stage Amplifier biased by Voltage-Combiners with Gain and Energy-Efficiency Enhancement, IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. PP, No. 99, pp. 1 - 1, March, 2017,
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N. Lourenço, R. M. Martins, A. Canelas, R. P. Póvoa, N. Horta, AIDA: Layout-aware analog circuit-level sizing with in-loop layout generation, Integration, the VLSI Journal, Vol. 55, No. 09, pp. 316 - 329, September, 2016,
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R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Current-flow & Current-Density-aware Multi-Objective Optimization of Analog IC Placement, Integration, the VLSI Journal, Vol. --, No. --, pp. -- - --, June, 2016,
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R. M. Martins, N. Lourenço, N. Horta, Multi-objective optimization of analog integrated circuit placement hierarchy in absolute coordinates, Expert Systems with Applications, Vol. 42, No. 23, pp. 9137 - 9151, December, 2015,
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N. Lourenço, A. Canelas, R. P. Póvoa, R. M. Martins, N. Horta, Floorplan-aware analog IC sizing and optimization based on topological constraints, Integration, the VLSI Journal, Vol. 48, No. 1, pp. 183 - 197, January, 2015,
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R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Electromigration-aware analog Router with multilayer multiport terminal structures, Integration, the VLSI Journal, Vol. 47, No. 4, pp. 532 - 547, September, 2014,
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R. M. Martins, N. Lourenço, N. Horta, LAYGEN II—Automatic Layout Generation of Analog Integrated Circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 32, No. 11, pp. 1641 - 1654, November, 2013,
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R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Routing analog ICs using a multi-objective multi-constraint evolutionary approach, Analog Integrated Circuits and Signal Processing, Vol. 78, No. 1, pp. 123 - 135, June, 2013,
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31Papers in Conferences

R. P. Póvoa, R. M. Martins, N. Lourenço, A. Canelas, N. Horta, JG Goes, Artificial Neural Networks as an Alternative for Automatic Analog IC Placement, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, Vol., pp. -, July, 2019 | BibTex
N. Lourenço, E. Moutaye, R. M. Martins, A. Canelas, R. P. Póvoa, N. Horta, Hard and Soft Constraints for Multi-objective Analog IC Sizing Optimization, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, Vol., pp. -, July, 2019,
| Abstract | Full text (PDF 647 KBs) | BibTex
N. Lourenço, E. Afacan, R. M. Martins, F. P. Passos, A. Canelas, R. P. Póvoa, N. Horta, G. Dundar, Using Polynomial Regression and Artificial Neural Networks for Reusable Analog IC Sizing, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lausanne, Switzerland, Vol., pp. -, July, 2019,
| Abstract | Full text (PDF 908 KBs) | BibTex
N. Lourenço, J. Rosa, R. M. Martins, H. Aidos, A. Canelas, R. P. Póvoa, N. Horta, On the Exploration of Promising Analog IC Designs via Artificial Neural Networks, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, Vol., pp. 133 - 136, July, 2018,
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F. P. Passos, E. Roca, R. Castro-López, F. Fernández, R. P. Póvoa, R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Handling the Effects of Variability and Layout Parasitics in the Automatic Synthesis of LNAs, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Prague, Czech Republic, Vol., pp. -, July, 2018 | BibTex
T. Pessoa, N. Lourenço, R. M. Martins, R. P. Póvoa, N. Horta, Enhanced Analog and RF IC Sizing Methodology using PCA and NSGA-II Optimization Kernel, Design, Automation, and Test in Europe - DATE, Dresden, Germany, Vol., pp. 1 - 4, March, 2018,
| Abstract | Full text (PDF 1 MB) | BibTex
R. M. Martins, N. Lourenço, R. P. Póvoa, A. Canelas, N. Horta, F. P. Passos, R. Castro-López, E. Roca, F. Fernández, Layout-Aware Challenges and a Solution for the Automatic Synthesis of Radio-Frequency IC Blocks, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Taormina, Italy, Vol., pp. -, June, 2017,
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R. P. Póvoa, A. Canelas, R. M. Martins, N. Lourenço, N. Horta, JG Goes, Dynamic Voltage-Combiners Biased OTA for Low-Power High-Speed SC Circuits, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Taormina, Italy, Vol., pp. -, June, 2017 | BibTex
N. Lourenço, R. M. Martins, R. P. Póvoa, A. Canelas, N. Horta, F. P. Passos, R. Castro-López, E. Roca, F. Fernández, New Mapping Strategies for Pre-Optimized Inductor Sets in Bottom-Up RF IC Sizing Optimization, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Taormina, Italy, Vol., pp. -, June, 2017,
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F. P. Passos, R. C.-L. Castro-López, E. Roca, F. V. F, Fernández, R. M. Martins, N. Lourenço, R. P. Póvoa, A. Canelas, N. Horta, Systematic Design of a Voltage Controlled Oscillator using a Layout-Aware Approach, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Taormina, Italy, Vol., pp. -, June, 2017,
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A. Canelas, R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Efficient Yield Optimization Method using a Variable K-Means Algorithm for Analog IC Sizing, Design, Automation, and Test in Europe - DATE, Lausanne, Switzerland, Vol. N/A, pp. 1 - 6, March, 2017,
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A. Ferreira, N. Lourenço, R. M. Martins, N. Horta, Automated analog IC design constraints generation for a layout-aware sizing approach, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lisboa, Portugal, Vol. --, pp. 1 - 4, June, 2016,
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A. Canelas, R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Yield Optimization using K-Means Clustering Algorithm to reduce Monte Carlo Simulations, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lisbon, Portugal, Vol. n/a, pp. 1 - 4, June, 2016,
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R. M. Martins, A. Canelas, N. Lourenço, N. Horta, On-the-fly Exploration of Placement Templates for Analog IC Layout-aware Sizing Methodologies, IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Lisboa, Portugal, Vol. n/a, pp. 1 - 4, June, 2016 | BibTex
D. Neves, R. M. Martins, N. Lourenço, N. Horta, Design Automation Tasks Scheduling for Enhanced Parallel Execution of a State-of-the-Art Layout-Aware Sizing Approach, Design, Automation, and Test in Europe - DATE, Dresden, Germany, Vol. n/a, pp. 1 - 4, March, 2016,
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R. M. Martins, N. Lourenço, N. Horta, M. Santos, Embedding Fault List Compression Techniques in a Design Automation Framework for Analog and Mixed-Signal Structural Testing, Conference on Design of Circuits and Integrated Systems DCIS, Estoril, Portugal, Vol. n/a, pp. n/a - n/a, November, 2015,
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R. M. Martins, R. P. Póvoa, N. Lourenço, N. Horta, Exploring Design Tradeoffs in Analog IC Placement with Current-Flow & Current-Density Considerations, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. n/a, pp. n/a - n/a, September, 2015,
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R. M. Martins, N. Lourenço, A. Canelas, R. P. Póvoa, N. Horta, AIDA: Robust Layout-Aware Synthesis of Analog ICs including Sizing and Layout Generation, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Istanbul, Turkey, Vol. n/a, pp. n/a - n/a, September, 2015,
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R. M. Martins, N. Lourenço, N. Horta, Analog IC Placement using Absolute Coordinates and a Hierarchical Combination of Pareto Optimal Fronts, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Glasgow, United Kingdom, Vol., pp. -, June, 2015,
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B. Cardoso, R. M. Martins, N. Lourenço, N. Horta, AIDA-PEx: Accurate Parasitic Extraction for Layout-Aware Analog Integrated Circuit Sizing, IEEE PhD. Research in Microelectronics and Electronics - PRIME, Glasgow, United Kingdom, Vol., pp. -, June, 2015,
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R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Extraction and Application of Wiring Symmetry Rules to Route Analog Multiport Terminals, IEEE International Symp. on Circuits and Systems - ISCAS, Lisboa, Portugal, Vol. n/a, pp. 1945 - 1948, May, 2015,
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N. Lourenço, R. M. Martins, N. Horta, Layout-Aware Sizing of Analog ICs using Floorplan & Routing Estimates for Parasitic Extraction, Design, Automation and Test in Europe Conf., Grenoble, France, Vol. 0, pp. 1 - 6, March, 2015,
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R. P. Póvoa, R. Lourenço Lourenço, N. Lourenço, A. Canelas, R. M. Martins, N. Horta, LC-VCO Automatic Synthesis Using Multi-Objective Evolutionary Techniques, IEEE International Symp. on Circuits and Systems - ISCAS, Melbourne, Australia, Vol., pp. -, June, 2014 | BibTex
R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Electromigration-Aware and IR-Drop Avoidance Routing in Analog Multiport Terminal Structures, Design, Automation, and Test in Europe - DATE, Dresden, Germany, Vol. n/a, pp. 1 - 6, March, 2014,
| Abstract | BibTex
F.C. Cadete, N. Lourenço, M.B. Barros, R. M. Martins, N. Horta, A New Metaheuristc Combining Gradient Models with NSGA-II to Enhance Analog IC Synthesis, IEEE Congress on Evolutionary Computation - CEC, Cancun, Mexico, Vol., pp. -, June, 2013,
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R. M. Martins, N. Lourenço, A. Canelas, N. Horta, Multi-Port Multi-Terminal Analog Router based on an Evolutionary Optimization Kernel, IEEE Congress on Evolutionary Computation - CEC, Cancún, Mexico, Vol. n/a, pp. 2789 - 2796, June, 2013,
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F. Rocha, R. P. Póvoa, N. Lourenço, R. M. Martins, N. Horta, A New Metaheuristc Combining Gradient Models with NSGA-II to Enhance Analog IC Synthesis, IEEE Congress on Evolutionary Computation - CEC, Cancún, Mexico, Vol., pp. -, June, 2013 | BibTex
F.C. Cadete, R. M. Martins, N. Lourenço, N. Horta, Enhancing a Layout-Aware Synthesis Methodology for Analog ICs by Embedding Statistical Knowledge into the Evolutionary Optimization Kernel, Doctoral Conf. on Computing, Electrical and Industrial Systems - DOCEIS, Lisbon, Portugal, Vol., pp. -, April, 2013,
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R. M. Martins, N. Lourenço, N. Horta, Multi-Objective Multi-Constraint Routing of Analog ICs using a Modified NSGA-II Approach, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Seville, Spain, Vol. n/a, pp. 65 - 68, September, 2012,
| Abstract | BibTex
R. M. Martins, N. Lourenço, J.G. Guilherme, N. Horta, AIDA: Automated Analog IC Design Flow from Circuit Level to Layout, International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Seville, Spain, Vol. n/a, pp. 29 - 32, September, 2012,
| Abstract | BibTex
R. M. Martins, N. Lourenço, N. Horta, LAYGEN II – Automatic Analog ICs Layout Generator based on a Template Approach, Genetic and Evolutionary Computation Conf. - GECCO, Philadelphia, United States, Vol. n/a, pp. 1127 - 1134, July, 2012,
| Abstract | BibTex

Projects

Currently running projects1

Acronym	Name	Funding Agency	Start date	Ending date
AIDA-C	AIDA-C: Analog IC Optimizer	Thales Alenia Space	01-10-2013	01-11-2021

Closed Projects2

Acronym	Name	Funding Agency	Start date	Ending date
DISRUPTIVE	DISRUPTIVE - A Paradigm Shift in the Design of Analog and Mixed-Signal Nanoelectronic Circuits and Systems	FCT	01-04-2013	01-12-2016
OPERA	OPERA - Layout-Aware Analog IC Design Automation	IT/LA	01-03-2014	01-02-2016

Other Scientific Achievements

5Awards

R. M. Martins, A. Canelas, N. Lourenço, N. Horta, Best Paper Award at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), "On-the-fly exploration of placement templates for analog IC layout-aware sizing methodologies," , in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Lisboa, Portugal, June 2016., 01-06-2016
R. M. Martins, N. Lourenço, A. Canelas, R. P. Póvoa, N. Horta, 1st Ranked on “Design Automation Competition” at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), "AIDA: Robust Layout-Aware Synthesis of Analog ICs including Sizing and Layout Generation" at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Istanbul, Turkey., 01-09-2015
R. M. Martins, N. Lourenço, N. Horta, Silver Leaf Best Paper Award at IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME), “Analog IC Placement using Absolute Coordinates and a Hierarchical Combination of Pareto Optimal Fronts”, in IEEE Conference on PhD Research in Microelectronics and Electronics (PRIME), Glasgow, Scotland, June 2015., 01-07-2015
R. P. Póvoa, R. Lourenço Lourenço, N. Lourenço, A. Canelas, R. M. Martins, N. Horta, Best Student Paper Award Runner-Up at IEEE International Symp. on Circuits and Systems (ISCAS), LC-VCO Automatic Synthesis Using Multi-Objective Evolutionary Techniques, Melbourne, Australia., 01-06-2014
R. M. Martins, N. Lourenço, S. R. Rodrigues, J.G. Guilherme, N. Horta, Honourable Mention on “Design Automation Competition” at International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), “AIDA: Automated Analog IC Design Flow from Circuit Level to Layout”, in International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Seville, Spain, Sep. 2012., 01-09-2012

Other Contributions

3Conference Committees

International Conf. on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Conference co-chair, 2017
IEEE International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design - SMACD, Conference co-chair, 2016
IEEE PhD. Research in Microelectronics and Electronics - PRIME, Conference co-chair, 2016

IT Member Profile